Microprocessor Power Gate Zoning for Low-Transient Wake-Up
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Solution Overview
Problem
Power distribution in microprocessors can cause damage to gates and downstream components due to transient high current, low load conditions during wake-up events, leading to potential breakdowns and inefficiencies.
Innovation Solution
Implementing a staged power introduction method across multiple power gates and zones within a microprocessor partition, distributing the strain of wake-up events across a larger number of power gates, either during the same or different wake-up conditions, to reduce the risk of damage and expedite turn-on times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If power is supplied to all power gates simultaneously during wake-up, then turn-on time is reduced, but high current transient causes damage to gates and downstream components
Solution Approach 1:
The patent divides power gates into multiple zones and further segments them into groups, powering them sequentially rather than simultaneously. This segmentation allows the system to maintain faster turn-on times compared to traditional sequential methods while distributing the current transient across multiple smaller groups, reducing peak current stress on individual gates and downstream components.
Solution Approach 2:
The patent implements preliminary power distribution to specific zones and groups before fully activating all power gates. By pre-powering certain zones first and then activating others in a controlled sequence, the system prepares the power distribution network to handle transient currents more effectively, reducing damage risk while maintaining efficient wake-up performance.
2Productivity
If power is distributed to multiple power gates simultaneously, then power delivery efficiency is improved, but the strain on individual power gates increases leading to potential failure
Solution Approach 1:
The patent segments power gates into multiple zones and groups that can be powered in a distributed manner. This segmentation enables efficient power delivery across the microprocessor by activating multiple groups concurrently rather than sequentially, while each individual group experiences reduced current strain, extending power gate lifespan.
Solution Approach 2:
The patent applies different power distribution strategies to different zones and groups of power gates based on their specific locations and requirements. By tailoring the power activation sequence and grouping to local conditions, the system optimizes both power delivery efficiency and individual gate reliability, preventing any single gate from bearing excessive strain.
3Reliability
If traditional sequential power distribution is used, then component damage is reduced, but turn-on time and power delivery efficiency decrease
Solution Approach 1:
The patent segments the power distribution into multiple zones and groups, allowing parallel activation of multiple segments rather than strict sequential activation. This segmentation enables the system to protect components from damage while significantly reducing wake-up time compared to traditional sequential methods, as multiple groups can be powered simultaneously or in overlapping sequences.
Solution Approach 2:
The patent implements a periodic or phased power activation scheme where different groups of power gates are activated in alternating phases rather than all at once or in strict sequence. This periodic action distributes the current transient over time while maintaining high overall power delivery efficiency, reducing component stress without sacrificing wake-up performance.
Data Source
AI summary
Embodiments related to controlling power distribution within a microprocessor are provided. In one example, a microprocessor comprising a power supply is provided. The example microprocessor also includes a plurality of power gate zones configured to receive power from the power supply, each power gate zone including a plurality of power gates, where the power gates within any given one of the power gate zones are controlled by the microprocessor independently of its control of power gates within any other of the power gate zones. The example microprocessor is operative to cause power initially to be supplied to a first power gate in a first one of the power gate zones, power then to be supplied to a second power gate in a second one of the power gate zones, and power then to be supplied to a third power gate in the first one of the power gate zones.