Power-Gated Logic Clamping Without Isolation Cell Delay
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Solution Overview
Problem
Conventional semiconductor devices with power gating units experience slowed operation speeds due to the insertion of isolation cells, which delay signals and increase power consumption when the power gating unit is turned off, as they attempt to provide a predetermined logic level to combinational logic units.
Innovation Solution
A semiconductor device with a power gating unit, a combinational logic unit, and a clamping unit that directly connects the output electrode of the power gating unit to the input electrode of the combinational logic unit through a data line, where the clamping unit clamps the internal signal at a logic high or low level based on operation modes, eliminating the need for isolation cells and maintaining high operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an isolation cell is inserted between the power gating unit and the combinational logic unit to provide a signal having a predetermined logic level, then the logic level is maintained, but the operation speed is slowed due to signal delay
Solution Approach 1:
The patent extracts the isolation cell from the signal path between the power gating unit and combinational logic unit. Instead of inserting an isolation cell to maintain logic levels, the invention uses a clamping unit that directly clamps the output signal of the power gating unit, eliminating the isolation cell and its associated signal delay while maintaining logic level stability.
Solution Approach 2:
The patent introduces a clamping unit as a new intermediary component that directly clamps the output signal of the power gating unit. This clamping unit serves as a more efficient mediator compared to the traditional isolation cell, providing logic level stabilization without the signal delay penalty. The clamping unit includes clamp switches that can be controlled to clamp or release the output signal as needed.
2Reliability
If an isolation cell is inserted to maintain logic levels when power gating is off, then logic stability is improved, but power consumption increases
Solution Approach 1:
The patent implements a dynamic clamping mechanism where the clamping unit can be turned on or off based on the operation mode. During normal operation, the clamping unit is off and does not affect signal transmission. During standby mode, the clamping unit is activated to clamp the output signal at a predetermined logic level. This dynamic control allows the system to maintain logic stability only when needed, reducing unnecessary power consumption during active operation.
Solution Approach 2:
The patent discards the traditional isolation cell approach and recovers power efficiency by using a controllable clamping unit. The clamping unit is activated only during standby mode when logic level maintenance is required, and deactivated during normal operation when full signal transmission is needed. This selective activation pattern eliminates continuous power consumption associated with always-on isolation cells.
3Use of energy by moving object
If the power gating unit is turned off to reduce power consumption, then power efficiency is improved, but the output signal becomes floated with undetermined logic level
Solution Approach 1:
The patent applies preliminary action by activating the clamping unit before or simultaneously with turning off the power gating unit during standby mode. The clamping unit proactively clamps the output signal at a predetermined logic level (either logic high or logic low) before the power gating unit is fully disabled. This preliminary clamping action ensures that the output signal maintains a valid logic level even when the power gating unit is off, preventing floating state issues.
Solution Approach 2:
The patent converts the harmful effect of a floated output signal into a beneficial stable logic level by using the clamping unit. When the power gating unit is turned off, instead of leaving the output floating (which is harmful), the clamping unit actively pulls the output to a defined logic level. This transforms the potential problem of a floating signal into a benefit of having a well-defined logic level during standby mode.
Data Source
AI summary
A semiconductor device includes a power gating unit, a combinational logic unit and a clamping unit. The power gating unit is turned on to output an internal signal at an output electrode based on an input signal or turned off according to operation modes. The combinational logic unit includes an input electrode directly connected to the output electrode of the power gating unit through a data line, and generates an output signal based on the internal signal received through the data line. The clamping unit is turned on to clamp the internal signal at a logic high level or at a logic low level or turned off according to the operation modes. The semiconductor device clamps the output electrode of the power gating unit without degrading an operation speed of the semiconductor device.