Power-Gated Logic Circuit Layout Without Level Converters
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Solution Overview
Problem
Existing semiconductor devices face increased subthreshold current and complex wiring structures due to the need for level converting circuits when implementing power gating control, leading to signal delays and increased circuit size.
Innovation Solution
A semiconductor device configuration where a second logic circuit is power gated on either the high or low potential side is arranged between first and third logic circuits that are power gated on both sides, eliminating the need for level converting circuits and simplifying the power supply wiring structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating control is implemented with all power nodes connected to dummy power lines, then subthreshold current is reduced, but level converting circuits are required increasing device complexity
Solution Approach 1:
The patent segments the power supply system into main power lines and dummy power lines, with different connection strategies for different logic circuits. High potential side power nodes are connected to main power lines while low potential side power nodes are connected to dummy power lines, eliminating the need for level converting circuits while maintaining subthreshold current reduction.
Solution Approach 2:
Different logic circuits are assigned different power line connection configurations based on their specific requirements. Some logic circuits have high potential sides connected to main power lines, while others have low potential sides connected to dummy power lines, allowing each circuit to operate optimally without requiring universal level converting circuits.
2Reliability
If level converting circuits are added to amplify output signal amplitude, then signal level is maintained, but signal delay increases and critical path speed decreases
Solution Approach 1:
The patent extracts and removes the level converting circuits from the signal path by redesigning the power gate control architecture. By connecting high potential side power nodes to main power lines and low potential side power nodes to dummy power lines, the output signal naturally maintains the correct logic level without requiring additional amplification stages, thereby eliminating signal delay.
3Loss of energy
If dummy power lines are disconnected from main power lines in standby mode, then subthreshold current is reduced, but wiring structure becomes complex
Solution Approach 1:
The patent merges the power gating control functionality into the existing power supply architecture by integrating dummy power lines with main power lines through controlled connections. The high potential side uses main power lines while the low potential side uses dummy power lines, allowing both to be disconnected simultaneously in standby mode without requiring separate complex wiring structures.
Data Source
AI summary
A semiconductor device includes a first circuit block connected between first and second power lines, a logic circuit that receives an output signal of the first circuit block that is connected between the first power line and a fourth power line or a third power line and the second power line, and a second circuit block that receives an output signal of the logic circuit that is connected between the third and fourth power lines. In an active state, a first potential is supplied and in a standby state, a second potential lower than the first potential is supplied between the first and second power lines. In any of the active state and the standby state, the first potential is supplied between the third and fourth power lines. With this configuration, speeding-up of a critical path can be realized while maintaining a subthreshold current low.