Power-Gated Logic Output Sequencing to Prevent Mode-Switch Glitches
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Solution Overview
Problem
Power-gated logic circuits in semiconductor devices experience glitches when switching modes due to floating coupling nodes and leakage currents, leading to potential malfunctions in digital devices.
Innovation Solution
A semiconductor device design that includes power-gated logic circuits, a transmission unit, and a clocked latch unit, with sequentially activated power gating enable signals to stabilize output signals and prevent glitches during mode transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating is applied to reduce leakage current, then power consumption is reduced, but glitches occur during mode switching
Solution Approach 1:
The transmission gate is enabled before the power gating switch to pre-charge or pre-discharge the coupling node, and the clocked latch is enabled after the power gating switch to capture the stable output. This preliminary action prevents floating node glitches during mode switching by ensuring proper signal levels are established before power gating transitions.
Solution Approach 2:
The transmission gate and clocked latch act as intermediary elements between the power-gated logic circuit and the output terminal. These intermediaries buffer and condition the output signal, preventing direct transmission of glitches caused by power gating transitions to the downstream circuitry.
2Speed
If slim transistors are used to improve switching rate, then switching speed increases, but leakage current increases
Solution Approach 1:
Different transistor types are used in different locations within the circuit. The power gating switch and control logic transistors use thick gate oxide for low leakage, while the main logic circuit transistors use slim gate oxide for fast switching. This local differentiation allows each part of the circuit to have optimal transistor characteristics for its specific function.
3Device complexity
If power gating enable signals are activated simultaneously, then circuit operation is simplified, but glitches occur due to floating coupling nodes
Solution Approach 1:
The power gating control is segmented into multiple independently timed signals: the transmission gate enable signal, the power gating switch control signal, and the clocked latch enable signal. Each signal is activated at a different time to create a controlled sequence that prevents glitches while maintaining manageable circuit complexity through modular signal generation.
Data Source
AI summary
A semiconductor device includes: a power-gated logic circuit suitable for operating in response to a first power gating enable signal which is deactivated in a standby mode and activated in an active mode; a transmission unit suitable for selectively transmitting an output signal of the power-gated logic circuit to an output terminal in response to a third power gating enable signal; a clocked latch unit suitable for latching a signal of the output terminal in the standby mode and an initial stage of the active mode in response to a second power gating enable signal; and an internal circuit suitable for operating based on the signal of the output terminal, wherein the first to third power gating enable signals are sequentially activated.