Power-Gated Semiconductor Circuits With Retention Signal Isolation
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Solution Overview
Problem
The propagation of unknown values from non-retention circuits to retention circuits during power gating operations reduces the reliability of stored data in semiconductor devices.
Innovation Solution
Incorporating a retention circuit, a non-retention circuit, a clock management unit (CMU), and a power management unit (PMU) to manage and isolate signals, ensuring reliable operation and data retention by generating and controlling operation clocks and isolation signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power gating operation is performed to reduce power consumption, then power consumption is reduced, but unknown values from non-retention circuits may propagate to retention circuits reducing data reliability
Solution Approach 1:
The patent introduces an isolation circuit as an intermediary component between the non-retention circuit and the retention circuit. This isolation circuit includes isolation signals and logic gates that prevent unknown values from propagating from the non-retention circuit to the retention circuit during power gating operations, thereby maintaining data reliability while enabling power savings.
Solution Approach 2:
The patent divides the circuit into distinct segments: a non-retention circuit that loses state during power gating, a retention circuit that maintains state, and an isolation circuit that separates them. This segmentation allows each part to function independently with appropriate power management, preventing harmful value propagation while enabling selective power gating.
2Reliability
If isolation circuits are added to prevent unknown value propagation, then data reliability is improved, but device complexity increases
Solution Approach 1:
The isolation circuit serves as a compact intermediary that provides reliable value blocking using minimal logic components. By placing simple isolation logic (AND gates with control signals) at critical interfaces, the patent achieves reliable value prevention with minimal additional circuit complexity.
Solution Approach 2:
The patent applies isolation mechanisms selectively only at specific interfaces where unknown value propagation is problematic, rather than throughout the entire circuit. This localized approach to quality control maintains data reliability at critical points while minimizing overall circuit complexity.
Data Source
AI summary
A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.