Power Gating Transistors in Wiring Layers Using 2D Channels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face limitations in the size and number of power gating elements due to sharing substrate area with other elements, and increased wiring length and complexity when forming power gating elements on the substrate.
Innovation Solution
Incorporating power gating elements as transistors with channel portions made of two-dimensional (2D) semiconductor material within wiring layers, allowing for their distribution across multiple layers and reducing wiring length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating elements are formed on the semiconductor substrate in the front end of line, then power consumption is reduced, but the size and number of power gating elements are limited due to substrate area sharing
Solution Approach 1:
The patent transitions power gating elements from the substrate plane (2D) to the vertical wiring layer dimension (3D). Power gating elements are formed within wiring layers using vias and conductive structures, enabling placement in the vertical dimension without consuming substrate area. This allows significantly more power gating elements to be implemented while maintaining substrate availability for logic circuits.
2Reliability
If power gating elements are formed on the semiconductor substrate, then power gating function is achieved, but wiring length and complexity increase since connecting circuits must pass through power gating elements
Solution Approach 1:
The patent extracts power gating elements from the substrate plane and relocates them to the wiring layer structure. By forming power gating elements using via structures and conductive layers within the existing wiring architecture, the design separates power gating functionality from the substrate layout, allowing independent optimization of both logic circuit placement and power gating implementation.
3Adaptability or versatility
If power gating elements share substrate area with other semiconductor elements, then integration is achieved, but the size of power gating elements is limited
Solution Approach 1:
The invention moves power gating elements from the substrate plane to the vertical wiring dimension, eliminating area competition between power gating elements and logic circuits. Power gating elements are implemented as via-based structures within wiring layers, allowing full substrate area utilization for high-performance logic circuits while providing adequately sized power gating elements in the vertical dimension.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device includes a first semiconductor chip that includes a semiconductor substrate which includes a plurality of circuit elements and a wiring structure which is disposed on the semiconductor substrate, and the wiring structure includes a plurality of wiring layers and one or more power gating elements disposed in the plurality of wiring layers, and the power gating elements are transistors including channel portions, gate electrodes, source electrodes, and drain electrodes, and the channel portions include a two-dimensional semiconductor material.