Programmable Power Gating Transistors for Leakage and Aging Control
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Solution Overview
Problem
In high-density integrated circuits like microprocessors, oversized power gating transistors lead to wasted power due to increased leakage currents at high temperatures and over time, as they are sized to accommodate worst-case scenarios, resulting in unnecessary voltage increases and power consumption.
Innovation Solution
The solution involves dynamically adjusting the number of active power gating transistors based on usage time and temperature, using a transistor aging detector and temperature detector to control voltage drop, allowing for fine resolution control of circuit voltage and reducing leakage current by avoiding the need for oversized transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power gating transistors are oversized to accommodate worst-case power consumption and end-of-life degradation, then reliability is improved, but leakage current increases and power is wasted
Solution Approach 1:
The patent implements dynamic adjustment of the number of active power gating transistors based on real-time temperature sensing and aging detection. Instead of using a fixed oversized configuration, the system actively monitors circuit conditions and adjusts transistor activation accordingly, transitioning from a static to a dynamic architecture that adapts to changing operational requirements.
Solution Approach 2:
The system incorporates feedback mechanisms through temperature detectors and aging detectors that continuously monitor operational conditions. Based on this feedback, the control logic adjusts the number of active power gating transistors to maintain optimal performance while minimizing leakage, creating a closed-loop control system that responds to actual circuit state.
2Temperature
If power gating transistors are oversized to maintain sufficient current flow at high temperatures, then temperature stability is improved, but voltage drop increases and power consumption increases
Solution Approach 1:
The system dynamically adjusts the number of active power gating transistors based on real-time temperature sensing. When temperature is high, more transistors remain active to maintain current flow; when temperature is low, fewer transistors are active, reducing leakage and power consumption while maintaining adequate performance.
Solution Approach 2:
The patent changes the operational parameters of the power gating transistors by adjusting the number of active devices based on temperature conditions. This parameter adjustment allows the system to optimize between current flow capability and power consumption depending on the thermal state of the circuit.
3Duration of action of stationary object
If power gating transistors are oversized to accommodate end-of-life current degradation, then duration of action is improved, but leakage current increases during early operation
Solution Approach 1:
The system incorporates an aging detector that proactively monitors transistor degradation and predicts end-of-life conditions. Based on this preliminary detection, the control logic adjusts the number of active transistors before actual performance degradation occurs, extending the effective operational lifespan while minimizing early leakage current.
Solution Approach 2:
The aging detector provides continuous feedback on transistor health and degradation status. This feedback enables the system to dynamically adjust the number of active power gating transistors, maintaining optimal performance throughout the product lifecycle while minimizing leakage current during early operation when transistors are still strong.
4Power
If multiple power gating transistors are connected in parallel to provide sufficient current flow, then current capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the power gating transistor array into multiple independently controllable units. Instead of treating all transistors as a single block, the system can selectively activate individual transistors or groups based on current requirements, enabling fine-grained control over current flow while managing complexity through modular organization.
Solution Approach 2:
The system implements dynamic control over the parallel transistor configuration, adjusting the number of active transistors based on real-time power and temperature requirements. This dynamic approach allows the system to use fewer transistors when full current capability is not needed, reducing effective complexity while maintaining the option for full capability when required.
Data Source
AI summary
The number of power-gating transistors on an integrated circuit used for power reduction in a sleep mode is controlled during a wake state to adjust the current flow and hence voltage drop across the power-gating transistors as a function of aging of these transistors and/or a function of temperature of the integrated circuit. In this way, the supply voltage to the integrated circuit may be better tailored to minimize current leakage when the integrated circuit is young or operating at low temperatures.