Power Gating Cell Layout for Vertically Stacked MOSFET Integration
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of metal oxide semiconductor field effect transistors (MOSFETs) deteriorate, necessitating improved integration and electrical properties to maintain performance.
Innovation Solution
The semiconductor device incorporates a power gating cell with a power gate electrode surrounding channel patterns, global and local power lines, and separation patterns, along with vertically stacked transistors to enhance integration and electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOSFET size is scaled down to increase integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent implements vertically stacked transistors (3D stacking) where multiple transistor layers are stacked in the vertical direction perpendicular to the substrate. This dimensional transition from 2D planar to 3D vertical architecture increases device density without further scaling lateral dimensions, thereby maintaining operating characteristics while achieving higher integration.
Solution Approach 2:
The patent employs nested power gating cells where control transistors are embedded within the transistor stack structure. The power gating control transistor is positioned between source/drain regions and nests the channel structure, enabling power management functionality integrated within the vertical stack without occupying additional lateral space.
2Quantity of substance
If transistor size is reduced to increase integration, then packing density increases, but electrical properties deteriorate
Solution Approach 1:
The vertically stacked transistor configuration allows multiple transistor channels to be stacked in the vertical direction, increasing packing density by utilizing the third dimension. Each stacked transistor maintains its electrical properties through proper gate control, avoiding the degradation that would occur with lateral scaling.
Solution Approach 2:
The patent segments the transistor structure into multiple discrete stacked layers, each with its own gate electrode and channel region. This segmentation allows independent optimization of each transistor layer's electrical characteristics while achieving high overall packing density through vertical integration.
3Loss of energy
If power gating cell structure is added to manage power, then power management efficiency improves, but device complexity increases
Solution Approach 1:
The patent merges the power gating control transistor with the main transistor stack structure, sharing common source/drain regions and channel materials. This integration combines power management functionality with the existing transistor architecture, improving power efficiency without proportionally increasing structural complexity.
Solution Approach 2:
The power gating cell structure serves multiple functions: it provides power management control, acts as a structural template for vertical stacking, and enables both n-type and p-type transistor configurations. This multi-functionality reduces overall device complexity by using a unified structure for multiple purposes.
Data Source
AI summary
An example semiconductor device includes a lower wiring layer including lower wiring lines, an upper wiring layer including upper wiring lines, and a power gating cell between the lower and upper wiring layers. The power gating cell includes a first active region on a substrate and including first and second lower source/drain patterns and a first channel pattern connecting the first and second lower source/drain patterns with each other, a second active region on the first active region and including first and second upper source/drain patterns, and a power gate electrode surrounding the first channel pattern and extending in a first direction parallel to a top surface of the substrate. The lower wiring layer includes a global power line connected with the first lower source/drain pattern and a local power line connected with the second lower source/drain pattern.