Power Gating Circuit Reverse Body Biasing Leakage Reduction
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Solution Overview
Problem
Conventional power gating circuits experience undesired leakage currents during sleep mode, leading to increased power consumption due to the inability to effectively cut off power supply.
Innovation Solution
A power gating circuit design that includes a first transistor and a buffer, where the buffer applies a higher or lower power supply voltage to the gate of the first transistor based on leakage current measurements, reducing the leakage current and power consumption by selectively coupling the power supply lines to a virtual power supply line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional power gating circuit uses a power cut-off switch to reduce power consumption, then power consumption is reduced, but leakage current occurs through the switch even in sleep mode
Solution Approach 1:
The patent applies reverse body biasing by changing the voltage parameter of the body terminal relative to the source terminal. Specifically, the body is biased at a lower voltage than the source (e.g., body at 0V, source at 1.8V), creating a reverse body effect that reduces off-state leakage current through the power cut-off switch while maintaining low power consumption
2Object-generated harmful factors
If the power supply voltage is adjusted to reduce leakage current, then leakage current is reduced, but circuit size increases
Solution Approach 1:
The patent merges the body terminal connection of the power cut-off switch with the virtual power supply line. By connecting the body to the virtual power supply line rather than creating a separate body bias circuit, the design reduces the number of additional components and interconnects, thereby minimizing circuit size while achieving leakage current reduction through reverse body biasing
Data Source
AI summary
A power gating circuit in an integrated circuit, including a circuit block coupled to a virtual power supply line, includes a first transistor and a buffer. The first transistor is coupled between a first power supply line and the virtual power supply line, and has a body coupled to the first power supply line. The buffer buffers a control signal to apply the buffered control signal to the first transistor, and includes a second transistor having a source coupled to a second power supply line and a body coupled to the first power supply line.