Power Gating Circuit Timing to Prevent Floating Internal Nodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face challenges in efficiently managing power consumption during power-down modes, as existing power gating operations do not effectively control voltage supply and clock signals, leading to inefficiencies and potential degradation of internal circuit characteristics.
Innovation Solution
The implementation of a device comprising a power gating signal generation circuit, a clock interrupt signal generation circuit, and a shift clock generation circuit, which generate and manage power gating, clock interrupt, and shift clock signals to control voltage supply and clock operations, ensuring efficient power management and preventing electrical floating of internal circuit nodes during power-down modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power gating operation is performed to reduce power consumption, then power consumption is reduced, but internal circuit nodes may electrically float causing signal degradation
Solution Approach 1:
The patent applies preliminary action by setting the clock interrupt period to be longer than the power gating period in advance. This ensures that the clock signal is interrupted before the power gating operation completes, preventing electrical floating of internal circuit nodes. The timing relationship is predetermined and configured beforehand, so when power gating is initiated, the clock interrupt is already scheduled to occur at the appropriate moment, thus preventing signal degradation while maintaining power savings.
2Reliability
If clock signals are continuously supplied to maintain internal circuit operation, then signal integrity is maintained, but power consumption increases
Solution Approach 1:
The patent applies periodic action by implementing a clock interrupt mechanism that periodically stops the clock signal during power-down mode. Instead of continuously supplying the clock signal, the system interrupts it at predetermined intervals (with the clock interrupt period being longer than the power gating period). This periodic interruption reduces power consumption while still maintaining signal integrity during the active periods, as the internal circuits remain operational during non-interrupted phases.
3Use of energy by moving object
If power gating period is extended to maximize power savings, then power consumption is reduced, but clock signal management becomes complex
Solution Approach 1:
The patent simplifies signal management complexity by establishing a predetermined timing relationship between power gating and clock interrupt operations in advance. The clock interrupt period is configured to be longer than the power gating period before operations begin, creating a clear and simple timing hierarchy. This preliminary configuration eliminates the need for complex real-time coordination logic, as the relationship between the two operations is predetermined and straightforward to implement in hardware.
Data Source
AI summary
A device includes a power gating signal generation circuit, a clock interrupt signal generation circuit, and a shift clock generation circuit. The power gating signal generation circuit configured to generate a power gating signal based on a mode entry signal and a mode exit signal to perform a power gating operation. The clock interrupt signal generation circuit configured to generate a clock interrupt signal based on the mode entry signal and the power gating signal to perform a clock interrupt operation. The shift clock generation circuit configured to generate a shift clock signal supplied to an internal circuit based on the power gating signal and the clock interrupt signal.