Power Gating Clock Control for Stable Wake-Up Voltage
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Solution Overview
Problem
Conventional zigzag power gating circuits experience errors and abnormal operations due to floating currents when transitioning out of power-down mode, as the second power voltage and ground voltage may not reach target levels in time, leading to power consumption issues in portable electronic devices.
Innovation Solution
A power gating system that includes a logic circuit region with logic gates receiving a first gating clock signal, controlled by a power gating control circuit which stabilizes the internal power voltage based on chip select, command/address, and external clock signals, ensuring the activation period matches read and write operations to prevent power gating errors and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating is applied to reduce power consumption in power-down mode, then power consumption is reduced, but floating currents may be generated when transitioning out of power-down mode causing power gating errors
Solution Approach 1:
The patent applies preliminary action by generating a delayed power gating control signal that activates the power gating switch only after the internal power voltage has stabilized. The delay circuit waits for a predetermined time period after the power-down mode exit signal is generated, ensuring that the power voltage reaches its target level before the power gating switch is turned on, thereby preventing floating currents and power gating errors while still achieving power consumption reduction.
2Loss of energy
If the clock signal is maintained at low level in power-down mode, then floating current is prevented, but the logic gates cannot operate when transitioning out of power-down mode
Solution Approach 1:
The patent uses preliminary action by maintaining the clock signal at a low level during the stabilization period after power-down mode exit, then activating it only after the power voltage has stabilized. The delay circuit ensures that the clock signal transitions to high level only after the predetermined time has elapsed, allowing the power voltage to reach target levels first, thus preventing floating currents while enabling subsequent logic gate operations.
Solution Approach 2:
The patent applies periodic action by controlling the clock signal to transition between low and high levels in a controlled sequence. The clock signal remains low during the power stabilization period, then transitions to high level periodically after the delay, enabling logic gate operations only when the power voltage is stable, thus preventing floating currents while ensuring proper operation timing.
3Speed
If the power gating switch is activated immediately when transitioning out of power-down mode, then operation speed is improved, but floating currents are generated causing abnormal logic gate operations
Solution Approach 1:
The patent applies preliminary action by introducing a delay circuit that waits for the power voltage to stabilize before activating the power gating switch. The delay circuit generates a power gating control signal after a predetermined time period, ensuring that the internal power voltage has reached its target level before the power gating switch is turned on. This prevents floating currents and abnormal logic gate operations while maintaining relatively fast operation speed.
Data Source
AI summary
A power gating system includes a logic circuit region including at least one logic gate configured to receive a first gating clock signal. The power gating system also includes a power gating control circuit configured to generate the first gating clock signal which is controlled to start transition after stabilization of an internal power voltage according to a chip select signal, a command/address signal, and an external clock signal.