Digital Power Gating with Controlled Resume for State Retention
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Solution Overview
Problem
Conventional power gating techniques are inefficient as they either force full power gating, leading to data loss or require costly state retention mechanisms, and result in significant latency and performance overhead due to the need to store and retrieve state information during power-down and power-up cycles.
Innovation Solution
A digital power gating system with state retention capabilities, where the supply voltage is reduced to a target level to minimize leakage current while maintaining digital states, and then gradually increased back to normal operating voltage upon resume, using a controlled digital power gating control system that adjusts voltage levels and clock signals to ensure data retention and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If full power gating is applied to reduce power consumption, then leakage current is minimized, but data loss occurs and state retention mechanisms are required
Solution Approach 1:
The patent applies parameter changes by transitioning the circuit from full power mode to a reduced voltage level (VDD_MIN) that is sufficient to maintain digital states without requiring full operating voltage. This controlled voltage reduction minimizes leakage current while preserving data, eliminating the need for external state retention mechanisms.
2Loss of information
If state retention mechanisms are implemented to maintain data during power gating, then data integrity is preserved, but device complexity and cost increase
Solution Approach 1:
The circuit serves itself by using its own minimal power consumption at VDD_MIN to maintain digital states during idle periods. No external state retention mechanisms are required - the circuit naturally preserves its state through controlled under-voltage operation, thereby reducing device complexity and cost.
3Speed
If voltage is quickly restored to normal operating level after power gating, then resumption speed is improved, but current spikes and stability issues occur
Solution Approach 1:
The patent implements periodic action through a controlled, incremental voltage restoration process. Rather than immediately restoring full voltage, the system gradually increases voltage from VDD_MIN to the normal operating level (VDD_NORMAL) in controlled steps, allowing the circuit to stabilize at each stage and avoiding current spikes while maintaining reliable operation.
4Loss of energy
If voltage is reduced to minimize leakage current, then power consumption decreases, but the circuit cannot perform useful work during idle periods
Solution Approach 1:
The patent applies dynamics by enabling the circuit to dynamically switch between two operational states: full power mode for performing useful work and reduced voltage mode for minimizing power consumption during idle periods. The ability to quickly transition between these states allows the circuit to optimize its performance based on workload requirements.
Data Source
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AI summary
An integrated circuit including a global supply bus, a gated supply bus, and a digital power gating system with controlled resume. The digital power gating system includes gating devices and a power gating control system. Each gating device has a pair of current terminals coupled between the global supply bus and the gated supply bus and each has a control terminal. The power gating control system controls a digital control value which controls activation of the gating devices. The power gating control system is configured to successively adjust the digital control value to increase a voltage of the gated supply bus from a reduced voltage level to a normal operating voltage level in response to a resume indication. The reduced voltage level may be a state retention level or full power gating. Successive adjustment may be with constant or adjusted gain using a constant clock or a dynamically adjusted clock.