Fine-Grained Power Gating for Microprocessor Functional Units
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Solution Overview
Problem
As transistors in microprocessors scale beyond 32 nm, the weakening electric polarization field leads to increased static power leakage, which is a dominant power loss, and existing power gating technologies introduce significant power up latencies or are not fine-grained enough to effectively manage this issue.
Innovation Solution
Implementing a fine-grained power gating technology within a microprocessor's execution units, where a power controller unit determines when functional units are needed and powers them up only for the required clock cycles, eliminating static and dynamic power dissipation during idle periods without software awareness, using electronic switches and a power distribution network to minimize power up latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating is implemented to reduce static power dissipation, then power consumption is reduced, but power up latency increases significantly
Solution Approach 1:
The patent divides the power gating control into fine-grained segments by functional unit type (integer ALU, floating-point units, load/store units, etc.), allowing independent power management for each unit type. This segmentation enables selective activation of only the specific functional units needed for the current instruction, reducing both power consumption and unnecessary power-up latency for units that remain idle.
Solution Approach 2:
The system dynamically adjusts the power state of functional units based on real-time instruction decoding results. The power controller continuously monitors instruction types and dynamically transitions functional units between active and powered-down states, optimizing the balance between power savings and performance based on actual workload requirements.
2Productivity
If more functional units are added to increase instruction level parallelism, then instruction execution throughput is improved, but static leakage power dissipation increases
Solution Approach 1:
The patent applies different power states to different functional units based on their specific usage requirements. Instead of uniformly powering all functional units, the system applies power gating selectively to each unit type (integer ALU, floating-point multiply, floating-point add, etc.) based on whether it is currently needed, optimizing the local power quality for each component.
Solution Approach 2:
The system temporarily discards power to functional units when they are not immediately needed for instruction execution. The power controller can quickly recover and reactivate these units when subsequent instructions require them, enabling the processor to maintain high instruction level parallelism capability while minimizing static leakage power during periods when certain units are idle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power dissipation, extends battery life, and allows for more aggressive superscalar implementations by dynamically controlling the power state of functional units, thereby alleviating the power budget constraints and improving reliability and performance.
Implementation Method 1
A switch coupled to the functional unit and configured to limit a power up latency of the functional unit
Data Source
AI summary
In an embodiment, a functional unit control system includes an instruction decoder of a processor comprising a pipeline, the instruction decoder being configured to decode an instruction to be performed by the processor. The system further includes a power controller unit coupled to the instruction decoder, and a functional unit which may operate during execution stages of the processor's pipeline coupled to the power controller unit and the instruction decode stage. The power controller unit is configured to determine whether the functional unit should be used to perform at least part of the instruction based on data of the instruction decoder. The power controller unit is further configured to perform at least one of activating and deactivating the functional unit in accordance with the determination of whether the functional unit should be used.