Power Gating in Monolithic 3DICs to Reduce Interconnect Resistance
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Solution Overview
Problem
Three-dimensional integrated circuits (3DICs) face challenges in increasing device density and reducing power consumption due to the crowding of interconnects, which leads to increased metal line resistance and RC delay, limiting the allowable widths of metal lines and complicating routing.
Innovation Solution
The implementation of monolithic 3DIC structures with power gating cells (PGCs) that separate true and virtual power supply interconnects into different active layers, allowing for reduced interconnect competition and optimized routing, thereby decreasing metal line resistance and improving chip performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more devices are integrated into a chip to increase device density, then integration density improves, but interconnect crowding increases leading to higher metal line resistance and RC delay
Solution Approach 1:
The patent transitions from traditional two-dimensional interconnect routing to three-dimensional routing by utilizing multiple metal layers stacked vertically. This dimensional change allows interconnects to route signals in the vertical direction through via connections, reducing lateral crowding and resistance in any single metal layer while maintaining high device density on the chip surface.
2Adaptability or versatility
If the number and length of interconnections increase to support more devices, then device functionality improves, but RC delay and power consumption increase
Solution Approach 1:
By implementing multi-layer metal interconnect structures with vertical via connections, the patent enables shorter lateral interconnect paths while maintaining full circuit functionality. Signals can transition between layers to bypass congested routing regions, reducing overall path length and RC delay despite increased device count and complexity.
3Quantity of substance
If metal line widths are reduced to accommodate more interconnects in crowded areas, then interconnect density improves, but metal line resistance increases
Solution Approach 1:
The patent distributes interconnect routing across multiple vertical layers, allowing each metal layer to maintain adequate line widths for low resistance while achieving high overall interconnect density through the stacked configuration. Current can flow through parallel paths in different layers, effectively reducing resistance without requiring narrower lines in any single layer.
Data Source
AI summary
A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.