Power-Gating Router With Bypass Switch for On-Chip Interconnect
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Solution Overview
Problem
On-chip interconnect architectures in parallel computing chips consume a significant portion of the power budget and suffer from high wake-up latency due to power-gating techniques, leading to network latency and degraded performance.
Innovation Solution
A new router design incorporating a conventional router and a bypass switch, along with a unified virtual channel state table and power-gating control policy, where the bypass switch handles low-traffic data and powers off the router to conserve energy, reducing latency and improving scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power-gating technique is applied to reduce power consumption, then power saving is improved, but wake-up latency increases causing network latency and performance degradation
Solution Approach 1:
The router is segmented into two distinct components: a conventional router for handling intensive communication traffic and a bypass switch for handling non-intensive traffic. This segmentation allows the system to selectively activate only the necessary component, reducing wake-up latency for low-traffic scenarios while maintaining power-saving benefits.
Solution Approach 2:
The system dynamically switches between two operational modes: using the bypass switch for low-traffic conditions to minimize latency, and activating the conventional router for intensive traffic to handle higher loads. This dynamic adaptation resolves the contradiction by adjusting the active component based on real-time traffic conditions.
2Productivity
If conventional router is used to handle all traffic, then communication capacity is improved, but power consumption increases
Solution Approach 1:
Instead of always activating the full-capacity conventional router, the system applies partial action by using the simplified bypass switch for non-intensive traffic. This provides sufficient communication capacity for low-traffic scenarios while avoiding the excessive power consumption of the full router.
Solution Approach 2:
Different components are assigned different functional qualities: the bypass switch handles non-intensive traffic with minimal power consumption, while the conventional router handles intensive traffic when needed. This local differentiation optimizes the balance between communication capacity and power consumption.
Data Source
AI summary
With the advent of manycore architecture, on-chip interconnect connects a number of cores, caches, memory modules, accelerators, graphic processing unit (GPU) or chiplets in one system. However, on-chip interconnect architecture consumes a significant portion of total parallel computing chip power. Power-gating is an effective technique to reduce power consumption by powering off the routers, but it suffers from a large wake-up latency to resume the full activity of routers. Recent research aims to improve the wake-up latency penalty by hiding it through early wake-up techniques. However, these techniques do not exploit the full advantage of power-gating due to the early wake-up. Consequently, they do not achieve significant power savings. The present invention provides a new router architecture that remedies the large wake-up latency overheads while providing significant power savings. The invention takes advantage of a simple switch to transmit packets without waking up the router. Additionally, the technique hides the wake-up latency by continuing to provide packet transmission during the wake-up phase.