Power Gating Transistor Current Regulation for Semiconductor Wake-Up Latency
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Solution Overview
Problem
Conventional semiconductor chips experience varying wake-up latencies across internal blocks due to differences in current requirements for stabilizing drive voltages, leading to longer overall wake-up times as they wait for the block with the longest latency to reach a stable voltage.
Innovation Solution
Incorporating a system manager and current regulators, such as current mirrors, to control the current flowing through power gating transistors, allowing for variable current flow based on block activation states, thereby reducing wake-up latency by prioritizing current delivery to blocks that require more time to stabilize.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional power gating operation is conducted with a single power gating transistor, then power leakage is reduced, but wake-up latency increases because all internal blocks must wait for the block with the longest charging time to reach stable voltage
Solution Approach 1:
The patent divides the single power gating transistor into multiple power gating transistors, each dedicated to serving specific internal blocks. This segmentation allows independent current control for each block, enabling dense blocks to receive higher current while sparse blocks receive lower current, thus reducing overall wake-up latency without compromising power leakage reduction
Solution Approach 2:
The patent applies different current amounts to different internal blocks based on their individual characteristics. Each power gating transistor supplies a customized current level matched to the density and complexity of its served blocks, allowing each block to reach stable voltage at its optimal rate rather than being constrained by the slowest block
2Device complexity
If the same current path is used for all internal blocks, then device complexity is reduced, but wake-up latency increases due to uniform current supply not matching varying block requirements
Solution Approach 1:
The unified current path is segmented into multiple independent current paths, each controlled by a dedicated power gating transistor. This allows the system to maintain relatively simple device architecture while enabling differentiated current supply to match the varying requirements of different internal blocks
Solution Approach 2:
The patent introduces dynamic current control capability where each power gating transistor can independently adjust its current output based on the specific needs of served blocks. This dynamic adaptation allows the system to optimize wake-up performance without requiring overly complex static circuit design
Data Source
AI summary
A semiconductor chip may include an internal circuit, at least one power gating transistor, a system manager, and/or at least one current regulator. The at least one power gating transistor may be configured to switch a supply of at least one drive voltage into the internal circuit. The system manager may be configured to generate a control signal corresponding to an activation state of the internal circuit. At least one current regulator may be configured to control an amount of a current flowing through the at least one power gating transistor in response to the control signal.