Power-Gating Transistor Sizing via Delay Statistics
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Solution Overview
Problem
In deep sub-micron technology, the challenge is to minimize sub-threshold leakage current in CMOS IC devices while optimizing the capacity of power-gating transistors to balance current supply and chip area usage, as existing methods either result in excessive transistor size or insufficient drive current.
Innovation Solution
The method involves determining the capacity of power-gating transistors based on delay statistics by analyzing switching times and signal arrival times across logic gates, allowing for the reduction of transistor width to meet only the necessary current demands, thereby minimizing chip space and optimizing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the power-gating transistor is made wider to supply sufficient operating current, then the drive current capability is improved, but the chip area occupied by the transistor increases
Solution Approach 1:
The patent applies parameter changes by using delay statistics to determine the actual switching behavior of logic gates. By analyzing signal arrival times and switching patterns, the method identifies that not all gates switch simultaneously, allowing the power-gating transistor width to be optimized based on statistical probability rather than worst-case assumptions. This reduces the transistor width parameter while maintaining sufficient drive current for actual operating conditions.
2Area of stationary object
If the power-gating transistor is made narrower to reduce chip area, then the area usage is improved, but the drive current capability deteriorates
Solution Approach 1:
The patent transforms the transistor width parameter from a fixed worst-case design to a statistically optimized value. By changing the design parameter based on delay statistics and switching probability analysis, the method achieves smaller transistor width that still provides adequate drive current for the actual switching patterns observed in the circuit.
3Reliability
If the power-gating transistor is made wider to ensure sufficient current supply, then the reliability of current supply is improved, but the leakage current through the transistor increases
Solution Approach 1:
The patent applies parameter changes by optimizing the transistor width based on statistical analysis of switching patterns. By using delay statistics to determine actual switching behavior, the method identifies that narrower transistors suffice for reliable operation, thereby reducing leakage current while maintaining current supply reliability for the actual operating conditions.
4Object-generated harmful factors
If the power-gating transistor is made narrower to reduce leakage current, then the leakage current is reduced, but the ability to supply operating current deteriorates
Solution Approach 1:
The patent transforms the transistor width parameter from a conservative fixed value to a statistically optimized value. By analyzing delay statistics and switching patterns, the method determines the minimum sufficient width that reduces leakage current while maintaining adequate operating current supply capability based on actual circuit behavior rather than worst-case assumptions.
Data Source
AI summary
A low-leakage circuit design method involves determining a capacity of a power gating transistor using delay statistics, wherein the resulting power gating transistor has sufficient capacity to supply all of the current necessary to meet the demands of the powered design elements while minimizing an amount of chip space required to implement the power gating transistor. The capacity of the power gating transistor is determined by first estimating a capacity necessary to meet the demands of all design elements connected to the transistor. The design elements are then grouped according to input signal arrival time to determine an amount by which the estimated capacity of the gating transistor may be reduced without affecting operation of the design elements. Various grouping schemes are evaluated to determine an optimal grouping. The estimated transistor capacity is reduced according to the optimal grouping, and the power gating transistor is implemented accordingly.