Power-Glitch Detection Circuit With Backup Supply Latching
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Solution Overview
Problem
Existing power-glitch detection methods fail to effectively detect short-duration glitches due to weak discharging capability of MOSs, especially at lower supply voltages, leading to false negatives.
Innovation Solution
Incorporating a back-up power storage device, inverter, and NMOS switch to quickly react to power glitches, ensuring reliable detection by connecting the negative output terminal to the positive output terminal, and using a D flip-flop for detection confirmation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If MOSs are used for power-glitch detection, then the detection circuit can operate at lower supply voltages, but the discharging capability becomes weak leading to false negatives
Solution Approach 1:
The patent divides the detection circuit into multiple independent glitch detection units, each capable of autonomous operation. Each unit contains dedicated PMOS and NMOS transistors that work independently to detect glitches, preventing the weakness of individual MOS discharging capability from compromising overall detection reliability.
Solution Approach 2:
The patent introduces intermediate latching circuits and output terminals that mediate between the MOS discharge action and the final detection output. The latching mechanism holds the detection state, allowing the circuit to maintain reliable detection output even when individual MOS discharging capability is weak at low supply voltages.
2Device complexity
If the detection circuit uses simple MOS-based discharge mechanism, then the device complexity is low, but the detection speed for short-duration glitches is insufficient
Solution Approach 1:
The patent implements preliminary action by pre-charging capacitors and positioning transistors in optimal states before glitches occur. The circuit maintains readiness through pre-configured PMOS and NMOS networks, enabling immediate response to short-duration glitches without requiring complex high-speed circuitry.
Solution Approach 2:
The patent employs periodic charging and discharging cycles through the PMOS and NMOS transistors to create detection windows that actively scan for glitches. This periodic action enables the simple circuit structure to achieve adequate detection speed by rhythmically sampling the power supply condition.
3Reliability
If MOSs are tied as diodes to improve discharge capability, then the detection reliability improves, but the device complexity and circuit design become more complicated
Solution Approach 1:
The patent merges the functions of multiple transistors into unified glitch detection units where PMOS and NMOS work together in coordinated pairs. This merging achieves enhanced discharge capability and detection reliability without requiring separate diode-connected MOS structures, thereby avoiding increased device complexity.
Solution Approach 2:
The patent designs universal glitch detection units that can operate effectively across different supply voltage conditions without requiring specialized diode-connected configurations. The multi-functional transistor networks serve both discharge and detection purposes simultaneously, eliminating the need for additional complexity-inducing diode connections.
Data Source
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AI summary
A chip with power-glitch detection is provided, which includes a power terminal receiving power, an inverter, and a back-up power storage device coupled to the power terminal. The inverter has an input terminal coupled to the power terminal. The back-up power storage device transforms the power to back-up power. The inverter is powered by the back-up power when a power glitch occurs on the power terminal, and the power glitch is reflected at an output terminal of the inverter.