Power Grid Compiler for Integrated Circuit Design Automation

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Solution Overview

Problem

Conventional methods for creating and implementing power grids in integrated circuits (ICs) are labor-intensive and unsatisfactory, requiring manual coding of numerous low-level commands for each sub-chip and being impractical for incorporating changes, especially under tight design schedules.

Innovation Solution

A power grid compiler translates high-level descriptions into base-level commands to generate wires and vias, and a power grid optimizer uses Quality of Results (QOR) analytics to optimize and incrementally update the power grid, allowing for efficient generation and modification of power grids across multiple sub-chips and regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If manual coding of low-level commands is used for each sub-chip, then power grid can be implemented, but labor intensity and time consumption increase significantly

Engineering Contradiction:

Improveease of power grid implementationVSAvoidtime for power grid design

Core Design Contradiction:

Ease of manufactureVSLoss of time

Solution Approach 1:

A compiler is introduced as an intermediary tool that translates high-level power grid descriptions into low-level implementation commands. This eliminates the need for manual coding while maintaining implementation accuracy, directly resolving the contradiction between ease of manufacture and time consumption.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system enables automatic generation of power grid implementations through high-level descriptions that the compiler processes autonomously. This self-service mechanism reduces labor intensity and accelerates the design process without sacrificing implementation quality.

Inventive Principle:

Principle #25Self-service

2Ease of manufacture

If uniform one-size-fits-all power grid distribution is used, then implementation is simplified, but adaptability to different sub-chips and power domains is reduced

Engineering Contradiction:

Improveease of power grid distributionVSAvoidadaptability of power grid

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The high-level power grid description language enables specification of different power grid configurations for different sub-chips and power domains. Each region can have customized parameters such as voltage, current capacity, and layout specifications, allowing local optimization while maintaining overall system coherence through the compiler's unified processing.

Inventive Principle:

Principle #3Local quality

3Ease of repair

If manual changes are made to power grid portions, then specific modifications can be implemented, but entire grid must be regenerated manually

Engineering Contradiction:

Improveease of power grid modificationVSAvoidcomplexity of modification process

Core Design Contradiction:

Ease of repairVSDevice complexity

Solution Approach 1:

The power grid is divided into independent modular sections that can be individually modified through targeted high-level description changes. The compiler processes only the affected segments and performs incremental updates, eliminating the need to regenerate the entire grid and reducing both modification complexity and computational overhead.

Inventive Principle:

Principle #1Segmentation

4Adaptability or versatility

If more than 100 separate routines are coded for each sub-chip, then each sub-chip gets its own power grid, but the overall system complexity increases

Engineering Contradiction:

Improvecustomization of power gridsVSAvoidcomplexity of power grid system

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A single high-level power grid description language serves multiple sub-chips and power domains universally. The compiler automatically adapts this unified description to generate appropriate implementations for each specific sub-chip, eliminating the need for numerous separate routines while maintaining full customization capability through parameters and constraints in the high-level description.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10242145B1Optimizing a power grid for an integrated circuit

Publication Date: 2019.03.26 CADENCE DESIGN SYST INC

AI summary

The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain additional aspects, embodiments include a power grid optimizer for optimizing portions of a power grid based on analytics such as QOR analytics, and incrementally updating the power grid to include these optimized portions.