Power Grid Layout Openings for Semiconductor Failure Analysis
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Solution Overview
Problem
As integrated circuits become more complex, the areas to be tested are often obscured by conductive layers, making it difficult to detect emitted signals for failure analysis, as existing methods struggle to optimize the layout of conductive layers for effective testing without severing power lines or causing other design constraints.
Innovation Solution
A method is introduced to identify candidate areas for removing portions of the conductive layer, determining which areas can be opened without violating design constraints, using a process analogous to solving the N-coloring problem, and employing electronic design automation tools to optimize the layout and reduce IR drop in power lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conductive layers are added to support complex integrated circuits, then power distribution and signal routing are improved, but testing capability deteriorates due to obscured active regions
Solution Approach 1:
The conductive layer is segmented by creating openings (windows) at specific locations to expose active regions. The power grid is divided into segments separated by these openings, allowing testing signals to pass through while maintaining power distribution in other areas. This segmentation enables simultaneous power delivery and testing capability.
Solution Approach 2:
Different regions of the conductive layer are assigned different properties: areas with openings have testing access quality, while areas without openings maintain continuous power distribution quality. The opening locations are strategically selected to provide local testing access without compromising overall power grid functionality.
2Difficulty of detecting and measuring
If openings are created in conductive layers for testing, then testing accessibility is improved, but power line integrity deteriorates due to potential severing
Solution Approach 1:
The locations of openings are determined in advance during the design phase using automated algorithms that analyze the power grid layout. This preliminary planning ensures that openings are placed in locations that provide testing access while avoiding critical power line paths, preventing power line severing before fabrication.
Solution Approach 2:
The system uses feedback from power grid analysis to adjust opening locations. The algorithm evaluates the impact of potential openings on power line connectivity and iteratively refines the opening placement to maintain power line integrity while achieving testing accessibility goals.
3Productivity
If more openings are created to increase visible device areas, then testing capability is improved, but IR drop in power lines worsens
Solution Approach 1:
Instead of creating openings throughout the entire conductive layer, the system applies partial action by selecting specific locations for openings based on testing requirements and power grid constraints. The algorithm determines the minimum necessary openings to achieve adequate testing coverage while minimizing disruption to power lines and reducing IR drop.
Data Source
AI summary
In some embodiments, portions of a pattern, generated in a layout process, of a layer in an integrated circuit, such as those of a layer of metallic power lines in a power grid (PG), are removed after the layout process through a computer-implemented process analogous to solving the N-coloring problem. Through this post-processing removal process, pattern portions can be removed so as reduce the coverage of the layer in the fabricated integrated circuit to a desired extent without producing certain harmful effects, such as severing a powerline.