Power Grid and Standard Cell Co-Design via Via Staple Overlap
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Solution Overview
Problem
Current integrated circuit design techniques face challenges with power grid and standard cell co-design, particularly due to interference from via staples in metal layers, which complicates cell placement and signal routing.
Innovation Solution
The proposed solution involves a metal layer with a specific pitch, a gate electrode layer with a pitch ratio, and the use of via staples that overlap gate electrode elements, along with even and odd versions of standard cells placed to avoid interference with via staples, allowing for unaligned power rails and optimized signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If via staples are used to couple power rails with the metal layer, then power distribution is achieved, but interference with standard cell placement and signal routing occurs
Solution Approach 1:
The patent applies asymmetry by creating two distinct types of placement sites (even and odd) with different characteristics. Even placement sites have via staples positioned differently than odd placement sites, allowing standard cells to be placed without interference while maintaining power distribution through the via staples.
Solution Approach 2:
The patent segments the chip surface into alternating even and odd placement sites based on the intersection patterns of power rails and metal layers. This segmentation allows different placement strategies for different regions, resolving the conflict between power distribution and cell placement.
2Ease of manufacture
If power rails are aligned with metal layers, then power distribution is simplified, but interference with signal routing occurs
Solution Approach 1:
The patent applies local quality by making the properties of placement sites location-dependent. Even placement sites have different via staple configurations than odd placement sites, allowing power rails to be aligned with metal layers in some regions while avoiding interference with signal routing in other regions.
3Area of stationary object
If standard cells are placed densely, then chip area utilization is improved, but interference with via staples increases
Solution Approach 1:
The patent introduces dynamic placement strategies where the placement of standard cells depends on the specific characteristics of each placement site (even or odd). This allows dense packing of standard cells while adapting to the local via staple configuration to avoid interference.
Data Source
AI summary
According to one general aspect, an apparatus may include a metal layer having a metal pitch between metal elements, and a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is a ratio of the metal pitch. The apparatus may include at least two power rails coupled, by via staples, with the metal layer, wherein the via staples at least partially overlap one or more of the gate electrode elements. The apparatus may include even and odd pluralities of standard cells, each respectively located in even/odd placement sites wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples.