Power Grid Layout Via Placement Optimization

Solution Overview

Problem

Existing power grid layout designs face challenges in standard cell placement due to via spacing violations, particularly in high-density architectures where cell vias can block power grid vias, necessitating post-route via insertion or restricting cell-level vias, which impact design density and area efficiency.

Innovation Solution

The implementation of via spacing methodologies that convert via pitch to a multiple of the horizontal placement pitch, defining landing zones and evaluating electro-magnetic current-resistance penalties, allowing for pre-route power rail via insertion and improving power grid layout designs by resolving spacing violations and optimizing via placement within cell architectures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If pre-route power rail via insertion is performed, then power grid layout compliance is improved, but via spacing violations occur due to cell vias blocking power grid vias

Engineering Contradiction:

Improvepower grid layout complianceVSAvoidvia spacing compliance

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent performs pre-route power rail via insertion by evaluating via spacing and identifying legal via locations before standard cell placement is finalized. This preliminary action allows the power grid layout to be established with proper via spacing compliance, avoiding conflicts with cell vias that will be placed later. The method calculates via pitch, determines legal via locations based on spacing rules, and inserts power grid vias at these predetermined locations before cell placement completes.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If post-route via insertion is performed to legalize via placement, then via spacing violations are resolved, but design density and area efficiency deteriorate

Engineering Contradiction:

Improvevia spacing complianceVSAvoiddesign density

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent performs pre-route power rail via insertion by evaluating via spacing and identifying legal via locations before standard cell placement is finalized. This preliminary action allows the power grid layout to be established with proper via spacing compliance, avoiding conflicts with cell vias that will be placed later. The method calculates via pitch, determines legal via locations based on spacing rules, and inserts power grid vias at these predetermined locations before cell placement completes.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If cell level vias are restricted to avoid blocking, then via spacing violations are prevented, but area efficiency and design density deteriorate

Engineering Contradiction:

Improvevia spacing complianceVSAvoidarea efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by evaluating via spacing requirements specifically in regions where power grid vias are needed. Instead of globally restricting all cell vias, the method identifies specific locations where power grid vias should be placed based on local spacing constraints. It calculates via pitch and determines legal via locations locally, allowing cell vias elsewhere to maintain high design density while ensuring power grid via spacing compliance in critical regions.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11288433B2Power grid layout techniques

Publication Date: 2022.03.29 ARM LTD

AI summary

Various implementations described herein refer to a method for providing a cell layout with a power grid line, track lines and vias. The method may include determining a cell placement pitch from architecture rules related to the cell layout. The method may include converting spacing for the vias in terms of the cell placement pitch to identify free regions on the track lines for placement of the vias. The method may include determining boundaries for the free regions based on the spacing of the vias from the power grid line and the track lines.