Power/Ground Interconnection Network for Reduced IR Drop
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Solution Overview
Problem
Conventional power/ground mesh interconnection schemes in integrated circuit chips result in high voltage drop (IR drop), increased power consumption, and reduced signal timing speed, while also limiting routing space for signal lines.
Innovation Solution
An improved power/ground interconnection network is implemented, featuring interleaved power and ground lines in the topmost metal layer with bump pads and extension portions, such as fishbone-shaped patterns, that reduce metal layer resistance and provide additional space for signal routing by optimizing the distribution of power and ground signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional power/ground mesh interconnection network is used in the topmost metal layers, then power and ground signals can be distributed to circuit blocks, but the metal layer resistance is high resulting in high IR drop and increased power consumption
Solution Approach 1:
The patent transitions from a two-dimensional mesh network to a three-dimensional power/ground network by adding vertical interconnection elements (via holes, trenches, and stacked conductive structures) that extend through multiple metal layers and substrate depths, creating additional current paths and reducing resistance in the power delivery network
Solution Approach 2:
The patent implements nested conductive structures where conductive plugs are embedded within conductive blocks, which are themselves surrounded by additional conductive layers, creating concentric current paths that reduce overall resistance and provide redundant power delivery channels
2Reliability
If a conventional power/ground mesh interconnection network is used in the topmost two or three levels of the interconnection metal layers, then power and ground routing can be established, but routing space for signal lines is significantly limited
Solution Approach 1:
The patent moves power and ground routing from the topmost metal layers to deeper substrate levels by creating vertical power/ground channels through via holes and trenches, thereby freeing up the top metal layers for signal routing and increasing available routing space
Solution Approach 2:
The patent segments the power/ground network into vertical channels distributed throughout the substrate, with each channel serving localized circuit blocks, thereby reducing the need for extensive horizontal power/ground traces in the top metal layers and freeing space for signals
3Reliability
If a conventional power/ground mesh interconnection network is used, then power distribution can be achieved, but the IR drop is high resulting in reduced signal timing speed
Solution Approach 1:
The patent creates nested conductive structures with multiple concentric current paths where inner conductive elements are surrounded by outer conductive layers, providing parallel current flow paths that reduce overall resistance and minimize IR drop to maintain signal timing speed
Data Source
AI summary
An integrated circuit chip includes a power/ground interconnection network in a topmost metal layer over a semiconductor substrate and at least a bump pad on/over the power/ground interconnection network. The power/ground mesh interconnection network includes a first power/ground line connected to the bump pad and extending along a first direction, and a connection portion connected to the bump pad and extending along a second direction.