Redistribution Power-Ground Layout for Flexible Chip Routing
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Solution Overview
Problem
Existing power and ground networks in integrated circuit components, particularly in redistribution structures, lack flexibility due to the use of pre-designed macros that occupy entire chip areas, limiting the routing of other features.
Innovation Solution
Designing power-ground networks with pre-designed macros in upper layers and leaving lower layers free for other features, combined with redundant vias and a shortest-path scheme to reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If pre-designed power-ground macros are used in redistribution structures, then design efficiency and ease of manufacture are improved, but design flexibility and area utilization deteriorate because entire chip areas are occupied and cannot be used for routing other features
Solution Approach 1:
The power-ground network is divided into two separate layers: upper layers contain pre-designed power-ground macros for ease of manufacture, while lower layers are freed for routing other features. This segmentation allows each layer to serve its specific function without interfering with the other, resolving the contradiction between manufacturing ease and design flexibility.
Solution Approach 2:
The solution moves the power-ground macros to upper layers, utilizing the vertical dimension (layer stacking) to separate power-ground routing from signal routing. This dimensional separation allows both power-ground networks and other features to coexist in the same chip area without conflict, maintaining both manufacturing efficiency and design flexibility.
2Ease of manufacture
If pre-designed power-ground macros are used, then manufacturing process is simplified, but chip area utilization worsens because the entire macro area cannot be used for other features
Solution Approach 1:
By segmenting the power-ground network into upper layers (with macros) and lower layers (for other routing), the chip area is effectively utilized without conflict. The vertical separation allows maximum area usage while maintaining manufacturing simplicity.
Solution Approach 2:
The solution exploits the third dimension (vertical layering) to resolve the area conflict. Power-ground macros occupy upper layers while lower layers remain available for other features, achieving high chip area utilization without compromising manufacturing ease.
3Power
If power-ground macros extend into lower layers, then power delivery is strengthened, but design flexibility deteriorates because lower layers cannot be used for other features
Solution Approach 1:
The power-ground network is segmented into upper layers (containing macros for power delivery) and lower layers (freed for other routing). This segmentation ensures strong power delivery through dedicated upper layer macros while maintaining design flexibility in the lower layers.
Solution Approach 2:
By confining power-ground macros to upper layers and utilizing lower layers for other features, the solution achieves both strong power delivery (through dedicated upper layer macros) and design flexibility (through available lower layers), resolving the contradiction via vertical dimensionality.
4Reliability
If redundant vias and shortest-path scheme are implemented, then power path resistance is reduced, but device complexity increases
Solution Approach 1:
The redundant vias and shortest-path routing are planned and implemented in advance during the design phase. This preliminary action ensures optimal power delivery paths are established before manufacturing, reducing resistance while maintaining manageable complexity through systematic design.
Solution Approach 2:
The solution optimizes the via density and routing paths by changing the structural parameters of the power-ground network. Redundant vias provide multiple parallel paths, effectively reducing resistance through parameter optimization rather than increasing overall device complexity.
Data Source
AI summary
A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.