Centralized Power Hold-Off Circuit for SSD Backup During Power Loss
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Solution Overview
Problem
Existing power management systems for low form factor memory devices, such as BGA, in automotive and embedded systems, face challenges with complex and expensive capacitor designs that are necessary for power backup during abrupt power loss events, leading to excessive noise and high costs.
Innovation Solution
A power hold-off circuit comprising a step-up regulator, step-down regulator, and power hold-off capacitors, which charges components requiring backup during voltage drops, allowing for optimized power management and reduced noise by centralizing the power hold-off circuitry, thereby eliminating the need for onboard capacitance in SSDs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitor designs are used for power backup during abrupt power loss events, then power backup capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent divides the power management system into two segments: a centralized power hold-off circuit located in the host system that handles power backup, and simplified SSD devices without onboard capacitance. This segmentation allows the complex capacitor design to be centralized in one location while keeping individual SSD devices simple.
Solution Approach 2:
The patent merges the power backup functionality into a centralized power hold-off circuit that serves multiple SSD devices simultaneously. Instead of each SSD having its own capacitance, the system combines power backup resources centrally, reducing overall complexity and cost while maintaining reliability.
2Reliability
If onboard capacitance is added to individual SSD devices, then power backup is improved, but electromagnetic interference and noise increase
Solution Approach 1:
The patent extracts the capacitance components from individual SSD devices and relocates them to a centralized power hold-off circuit in the host system. This extraction eliminates the source of electromagnetic interference and noise at the device level while preserving the power backup function centrally.
3Reliability
If complex capacitor designs are implemented, then power backup during voltage drops is improved, but cost increases
Solution Approach 1:
The centralized power hold-off circuit serves as a universal power backup solution for multiple SSD devices simultaneously. Instead of each device requiring its own expensive capacitor design, one multi-functional circuit provides backup power to the entire system, significantly reducing per-device cost while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides efficient power backup for low form factor devices with reduced electromagnetic interference, lower costs, and optimized power management, ensuring emergency data storage operations are completed before power loss without the need for additional capacitance on individual devices.
Implementation Method 1
a step-up regulator configured to increase voltage from the battery
Implementation Method 2
one or more power hold-off capacitors configured to charge components requiring backup when the voltage from the battery drops below a voltage threshold
Implementation Method 3
a step-down regulator configured to decrease voltage from the power hold-off capacitors
Data Source
AI summary
Implementations described herein relate to a power hold-off circuit and power hold-off circuit operation. In some implementations, a system may include a battery, a first pre-regulator that is connected to a first set components, a second pre-regulator that is connected to a second set of components, a second diode, and a power hold-off circuit. The power hold-off circuit may include a step-up regulator, a step-down regulator, one or more power hold-off capacitors, and a first diode. In some implementations, the second pre-regulator and the step-up regulator may be connected in parallel. In some other implementations, an output of the second pre-regulator may be connected to an input of the step-up regulator.