Power Supply IC Fault Delay Circuit for Accurate Fault Reset
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Solution Overview
Problem
Existing power supply semiconductor integrated circuits (ICs) fail to accurately detect and resolve open-circuit and short-circuit faults due to insufficient discharge time of the delay-setting capacitor, leading to incorrect fault detection signals.
Innovation Solution
Incorporating a delay circuit with a constant current source, discharge switch, and voltage comparator to delay and accurately capture fault detection signals, preventing error pulses when faults are resolved, and including a latch circuit to hold the output of the delay circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay circuit with a delay-setting capacitor is used to delay fault detection signals, then error pulses are prevented during rush current, but the capacitor does not have enough discharge time when faults are resolved, causing incorrect fault detection signals
Solution Approach 1:
The patent applies dynamics by making the discharge time of the delay-setting capacitor dynamic rather than fixed. The discharge time is adjusted based on the operational state of the regulator: during normal operation, the capacitor discharges completely to prepare for fault detection, while during fault conditions, the discharge is controlled to maintain proper timing. This dynamic adjustment resolves the contradiction between preventing error pulses and ensuring sufficient discharge time for accurate fault detection.
Solution Approach 2:
The patent changes the parameter of discharge time based on operational conditions. By controlling the discharge switch to adjust the discharge time constant, the system adapts the delay circuit's behavior to different states (normal operation vs. fault condition). This parameter change allows the capacitor to have adequate discharge time when needed while preventing error pulses during rush current conditions.
2Reliability
If the delay-setting capacitor voltage increases to a high level, then the delay function works during activation, but the capacitor cannot discharge in time when load is connected, causing false error pulse output
Solution Approach 1:
The discharge speed of the delay-setting capacitor is made dynamic through control of the discharge switch. During normal operation when the load is connected, the discharge switch is controlled to enable rapid discharge of the capacitor, ensuring it can discharge in time and prevent false error pulses. During fault conditions, the discharge is controlled to maintain the delay function. This dynamic control of discharge speed resolves the contradiction between reliable fault detection and fast discharge capability.
3Difficulty of detecting and measuring
If fault detection circuits are added to detect open-circuit and short-circuit faults, then fault detection capability is improved, but error pulses are generated when faults are resolved due to timing issues
Solution Approach 1:
The discharge switch acts as an intermediary between the fault detection circuits and the delay-setting capacitor. It mediates the timing relationship by controlling when the capacitor discharges, ensuring that fault detection signals are generated at the correct moments. This intermediary control prevents error pulses from being generated when faults are resolved, while maintaining the ability to detect both open-circuit and short-circuit faults accurately.
Solution Approach 2:
The system uses feedback from the operational state to control the discharge switch. The control circuit monitors the operational conditions and adjusts the discharge timing accordingly, creating a feedback loop that ensures fault detection signals are generated only when appropriate. This feedback mechanism eliminates false error pulses while maintaining comprehensive fault detection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents error pulses on fault detection signals during fault resolution, ensuring accurate detection of open-circuit and short-circuit faults in power supply ICs, such as regulator ICs and power supply switch ICs.
Implementation Method 1
a constant current source for charging a delay capacitor
Implementation Method 2
a discharge switch for discharging the delay capacitor
Implementation Method 3
a voltage comparator circuit that compares a voltage across the delay capacitor and a predetermined voltage
Data Source
AI summary
A power supply semiconductor integrated circuit includes an output transistor, a control circuit, a first-fault detection circuit, a second-fault detection circuit, a delay circuit, and a latch circuit. The output transistor is connected between a voltage-input terminal to which a DC voltage is input and a voltage-output terminal. The control circuit controls the output transistor. The first-fault detection circuit detects a first fault. The second-fault detection circuit detects a second fault different from the first fault. The delay circuit delays an output of the first-fault detection circuit and an output of the second-fault detection circuit. The latch circuit captures and holds an output of the delay circuit. The delay circuit includes: a constant current source for charging a delay capacitor; a discharge switch for discharging the delay capacitor; and a voltage comparator circuit that compares a charge voltage across the delay capacitor and a predetermined voltage.