Power Management IC Layout Using Front-Back Regulator Placement
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Solution Overview
Problem
Current semiconductor device power supply systems for high-power embedded systems, such as in-vehicle SoC, face challenges with increased mounting area and inefficient power supply path usage due to the large number of components and through-holes required, leading to reduced current flow and increased impedance in multi-layered power supply patterns.
Innovation Solution
The solution involves arranging multiple regulator circuits on both the front and back surfaces of the system board, with a unique power supply path for each layer and shared through-holes to minimize the area occupied by the regulator circuit and reduce the number of components, thereby optimizing current flow and impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If switching regulators with high conversion efficiency are used for large current power supply, then power conversion efficiency is improved, but the mounting area increases due to large capacitors, inductors, and capacitors for switching noise suppression
Solution Approach 1:
The patent transitions from planar 2D arrangement of power supply components to 3D vertical stacking by forming power supply patterns in multiple layers (first power supply pattern in first layer, second power supply pattern in second layer). This multi-layer configuration allows capacitors and inductors to be distributed across different layers, significantly reducing the mounting area on each individual layer while maintaining the required component count and power conversion efficiency.
2Loss of time
If multi-phase power supply is used to shorten response time, then response time is improved, but the mounting area increases due to multiple phases requiring more components
Solution Approach 1:
The patent implements multi-phase power supply by distributing phases across multiple layers vertically. The first power supply pattern in the first layer and the second power supply pattern in the second layer can represent different phases, allowing multi-phase operation to be achieved in the vertical dimension rather than requiring horizontal expansion, thus shortening response time without proportionally increasing mounting area.
3Reliability
If many through holes are used to connect multiple layers of power supplies, then power supply connectivity between layers is improved, but the board area is reduced due to increased number of through holes required for high current
Solution Approach 1:
The patent segments the power supply connection path into multiple independent layers, with the first power supply pattern in the first layer and the second power supply pattern in the second layer. This segmentation allows current to be distributed across multiple parallel paths through the layers, reducing the current burden on individual through holes and allowing larger board area to be utilized effectively.
4Power
If power supply pattern is arranged in multiple layers, then power supply capacity is improved, but the use efficiency of power supply pattern in far layer decreases due to increased resistance and inductance
Solution Approach 1:
The patent applies local quality by optimizing the configuration of power supply patterns in different layers. The first power supply pattern in the first layer and the second power supply pattern in the second layer are designed with appropriate trace widths, spacing, and connection points to minimize resistance and inductance. This ensures that even power supply patterns in farther layers maintain high current flow efficiency and low impedance, maximizing the use efficiency of all layers.
Data Source
AI summary
Semiconductor device has a regulator circuit having an even number of switching regulators that generate output power from an input power supply and a power management IC that controls the output potential generated by the switching regulator. semiconductor device is characterized in that a group of half of the even number of switching regulators is arranged on a first surface of semiconductor device system board, and a group of switching regulators, which is the remaining half, is arranged on a second surface that is in front-back relation with the first surface. This semiconductor device reduces semiconductor device board-area (pattern-resource).