Power Converter IC Layout With Vertical Paths for Lower Parasitics
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Solution Overview
Problem
Power converters face significant parasitic losses due to high current paths, which reduce efficiency and are exacerbated by space constraints and the need for larger inductors, especially in buck converters.
Innovation Solution
The use of a charge-pump converter to step down input voltage before it reaches the buck converter, combined with vertically oriented conductive paths and adjacently placed output terminals, allows for the use of smaller chip inductors and coupled inductors, reducing parasitic effects and optimizing space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional power converter design is used, then power conversion function is achieved, but parasitic losses are high due to high current paths
Solution Approach 1:
The patent transitions from lateral current paths to vertical current paths by stacking metal regions across multiple layers (M1, M2, M3, M4) above the active regions. This dimensional change reduces the current path length and parasitic losses by utilizing the vertical dimension of the integrated circuit structure.
Solution Approach 2:
The patent divides the power converter into separate functional blocks (charge-pump converter and buck converter) with dedicated metal region configurations for each. This segmentation allows independent optimization of current paths for each converter type, minimizing parasitic losses in high-current paths.
2Power
If larger inductors are used to handle high current, then power conversion capability is improved, but device area increases
Solution Approach 1:
The patent places the charge-pump converter inside or adjacent to the buck converter structure, with shared metal regions and coupled inductors. This nesting allows the system to achieve high power capability through voltage multiplication while using smaller inductors, reducing the overall device area.
Solution Approach 2:
The patent combines the charge-pump converter and buck converter into a single integrated circuit structure with shared metal regions (M3, M4) and coupled inductors. This merging allows both converters to work together to achieve high power capability while minimizing the total area required.
3Loss of energy
If charge-pump converter is added to step down voltage, then parasitic losses are reduced, but device complexity increases
Solution Approach 1:
The patent designs the metal regions (M1, M2, M3, M4) to serve multiple functions: they provide current paths for both the charge-pump converter and the buck converter, and the coupled inductors serve both converters. This multi-functionality reduces device complexity by avoiding duplicate structures.
Solution Approach 2:
The patent uses asymmetric metal region configurations where M3 and M4 extend laterally to form coupled inductors for both converters, while M1 and M2 are positioned differently for each converter. This asymmetric design allows the charge-pump converter to reduce parasitic losses without requiring a completely symmetric duplicate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes parasitic losses, enhances power conversion efficiency, and reduces the physical size of the power conversion system by utilizing smaller inductors and optimizing PCB layout.
Implementation Method 1
The use of a charge-pump converter to step down input voltage before it reaches the buck converter
Implementation Method 2
vertically oriented conductive paths and adjacently placed output terminals, allows for the use of smaller chip inductors and coupled inductors, reducing parasitic effects
Data Source
AI summary
Disclosed embodiments include methods, apparatuses, integrated circuits, and circuit boards for power conversion with reduced parasitics. The apparatuses include an integrated circuit for power conversion. The integrated circuit includes a plurality of power transistors and a plurality of metal regions coupled to the power transistors. A first portion of the metal regions are coupled to source regions of the power transistors. A second portion of the metal regions are coupled to drain regions of the power transistors. The first and second portions have at least one of substantially equal numbers of metal regions, substantially equal resistances, or balanced distributions of metal regions.