Power Impedance Measurement Circuit for PDN Bounce Profiling
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Solution Overview
Problem
High-performance computing (HPC) circuits face challenges in power delivery network stability due to large current consumption, leading to power or ground bounce noise and signal integrity issues, which can cause components to malfunction, and existing power impedance measurement methods face timing and area overhead limitations.
Innovation Solution
The implementation of equivalent-time sampling (ETS) methods for power delivery network (PDN) profiling, using a dual-mode power impedance measurement system that combines time-domain and frequency-domain sensing, with a voltage-controlled oscillator (VCO) and edge samplers to accurately estimate power voltage drops across IC components, allowing for robust PDN modeling and impedance measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stable power delivery network is required to minimize power or ground bounce noise, then signal integrity is improved, but device complexity increases due to the need for additional monitoring circuits
Solution Approach 1:
The patent combines time-domain sensing and frequency-domain sensing circuits into a unified power impedance measurement system. The time-domain sensing circuit measures voltage drops during transient events, while the frequency-domain sensing circuit measures impedance across different frequency ranges. By merging these two sensing approaches, the system achieves comprehensive PDN characterization without requiring separate independent monitoring systems, thus improving signal integrity while controlling device complexity.
Solution Approach 2:
The power impedance measurement system is designed to perform multiple functions: it can operate in both time-domain and frequency-domain modes, measure voltage drops, calculate impedance values, and characterize PDN behavior under different operating conditions. This multi-functional design allows a single system to address various signal integrity issues without requiring multiple specialized circuits, thereby improving reliability while managing complexity.
2Measurement precision
If timing resolution is improved to accurately capture power voltage waveforms, then measurement precision is improved, but timing constraints become more stringent
Solution Approach 1:
The system dynamically switches between time-domain sensing mode for capturing transient voltage drops with high timing resolution and frequency-domain sensing mode for measuring impedance characteristics. By making the sensing mode dynamic rather than static, the system can achieve high measurement precision when needed while avoiding the continuous timing constraint overhead, thus improving timing resolution while managing device complexity.
Solution Approach 2:
The patent changes the operating parameters of the sensing system by switching between different sensing modes (time-domain and frequency-domain) and adjusting measurement frequencies. This allows the system to optimize timing resolution for specific measurement needs without maintaining continuously stringent timing constraints across all operations, thereby improving measurement precision while controlling the complexity of timing management.
3Area of stationary object
If area overhead is reduced by minimizing extra sensing components, then manufacturing cost is reduced, but measurement capability may be compromised
Solution Approach 1:
The patent segments the power impedance measurement functionality into two distinct sensing circuits: a time-domain sensing circuit for measuring voltage drops during transients and a frequency-domain sensing circuit for measuring impedance across frequency ranges. Each segment is optimized for its specific function with minimal area overhead, while together they provide comprehensive measurement capability. This segmentation allows the system to maintain measurement precision without requiring a single large monolithic sensing circuit.
Solution Approach 2:
Instead of implementing a full-spectrum sensing circuit that would require excessive area, the patent uses partial sensing approaches: time-domain sensing captures critical transient events, and frequency-domain sensing measures impedance at selected frequency points. This partial sensing strategy achieves sufficient measurement precision for PDN characterization while minimizing the area overhead compared to a comprehensive continuous-spectrum sensing system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides high bandwidth and timing resolution, ensuring accurate reconstruction of power voltage waveforms, reducing noise and improving signal integrity, while minimizing area overhead and timing constraints, thus enhancing the stability and performance of HPC circuits.
Implementation Method 1
a voltage controlled oscillator (VCO), generating an oscillation signal according to a power voltage on the power rail
Implementation Method 2
an operation circuit, coupled to the VCO, receiving a sampling clock signal and the oscillation signal, sensing the power voltage to generate a sampled signal based on the sampling clock signal
Data Source
AI summary
An impedance measurement circuit and an operating method thereof are provided. The impedance measurement circuit includes a current source, a voltage controlled oscillator (VCO), an operation circuit, and a first delay circuit. The current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. The VCO is configured to generate an oscillation signal according to a power voltage on the power rail. The operation circuit is electrically connected to the VCO and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. The first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.