Power Impedance Measurement Circuit Using Equivalent-Time Sampling
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Solution Overview
Problem
High-performance computing (HPC) circuits face challenges in power delivery network stability due to large current consumption, leading to power or ground bounce noise and signal integrity issues, which are exacerbated by timing problems in digital circuits and area overhead from additional sensing components.
Innovation Solution
The implementation of equivalent-time sampling (ETS) methods for power delivery network (PDN) analysis, using a dual-mode power impedance measurement system that combines time-domain and frequency-domain sensing to accurately estimate power voltage drops across IC design circuits, incorporating a voltage-controlled oscillator, edge sampler, and accumulator to reconstruct waveforms and measure impedance efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power impedance measurement circuits are implemented to ensure robust PDN, then power delivery network stability is improved, but timing issues arise when trigger time and sampling time are too close
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing impedance values at multiple trigger time offsets before actual measurement. The system prepares a lookup table with pre-computed impedance data for various time offsets, allowing the measurement circuit to quickly retrieve and use appropriate values without performing real-time calculations that would cause timing conflicts between trigger and sampling operations.
2Measurement precision
If additional sensing components are added for power monitoring, then measurement precision is improved, but area overhead increases
Solution Approach 1:
The patent implements universality by designing a measurement circuit that performs multiple functions: it measures both time-domain impedance characteristics and frequency-domain impedance characteristics using the same hardware components. The VCO, edge samplers, and accumulator are configured to execute different measurement modes (time-domain ETS and frequency-domain swept-sine) without requiring separate dedicated sensing circuits for each mode, thereby reducing overall area overhead while maintaining measurement precision.
3Speed
If equivalent-time sampling is used for PDN analysis, then bandwidth and timing resolution are improved, but device complexity increases
Solution Approach 1:
The patent applies copying by creating multiple copies of the edge sampler circuitry, each configured to sample at different time offsets relative to the trigger signal. Instead of using a single complex high-speed sampler, the system uses several simpler sampler copies that operate at lower speeds but collectively achieve the equivalent of a high-bandwidth measurement through time-interleaved sampling and digital reconstruction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides high bandwidth and timing resolution, ensuring robust power delivery networks with reduced area and power overhead, effectively addressing signal integrity and noise issues in HPC circuits.
Implementation Method 1
a voltage controlled oscillator (VCO), generating an oscillation signal according to a power voltage on the power rail
Implementation Method 2
a first edge sampler, coupled to the VCO, receiving the oscillation signal from the VCO, and sampling the oscillation signal to generate a first sampled signal based on a sampling clock signal
Implementation Method 3
an accumulator, coupled to the operation circuit, receiving the operation result from the operation circuit, and accumulating the operation result to generate a measurement result
Data Source
AI summary
An impedance measurement circuit and an operating method thereof are provided. The impedance measurement circuit includes a current source, a voltage controlled oscillator (VCO), an operation circuit, and a first delay circuit. The current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. The VCO is configured to generate an oscillation signal according to a power voltage on the power rail. The operation circuit is electrically connected to the VCO and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. The first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.