Power Supply Interconnect Structure for Voltage Drop Reduction
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Solution Overview
Problem
The increasing integration density and chip size of semiconductor integrated circuits lead to higher power consumption, necessitating wider and longer power supply interconnects with lower resistance, but these are limited by manufacturing constraints, resulting in increased resistance values and voltage drops, which hinder performance.
Innovation Solution
The introduction of a power supply interconnect structure where empty spaces between interconnect segments are shifted relative to each other within the limits of interconnect lengths and areas, dispersing local resistance increases and reducing the influence on voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power supply interconnects are made wider and longer to reduce resistance, then power supply stability is improved, but manufacturing complexity increases due to interconnect length limitations
Solution Approach 1:
The power supply interconnect structure is divided into multiple segments arranged in a mesh pattern across different interconnect layers. Each segment has a controlled length within manufacturing limits, while the overall power delivery network achieves the required low resistance through the distributed parallel arrangement of these segments connected by vias.
Solution Approach 2:
The patent transitions from planar interconnect arrangements to a three-dimensional mesh structure utilizing multiple stacked interconnect layers. This vertical dimension allows power delivery paths to be distributed across layers, effectively reducing resistance without requiring excessively long interconnects within any single layer.
2Reliability
If power supply interconnects are made wider and longer to reduce resistance, then voltage drop is reduced, but interconnect length and area constraints are violated
Solution Approach 1:
Long power supply interconnects are segmented into multiple shorter sections distributed across a mesh pattern. Each segment maintains length within manufacturing constraints, while the cumulative effect of parallel current paths through the mesh structure achieves the desired reduction in overall voltage drop.
Solution Approach 2:
Multiple short interconnect segments across different layers are merged through via connections to form a distributed parallel network. This combining of segments creates equivalent low-resistance power delivery paths without requiring any single interconnect to exceed length limitations.
3Reliability
If power supply interconnects are made wider and longer to reduce resistance, then current supply stability is improved, but ease of manufacture decreases
Solution Approach 1:
The mesh interconnect structure implements local quality by creating regions of distributed power delivery across the chip surface. Each local mesh unit provides stable current supply to nearby logic elements, while the overall structure maintains manufacturability through standardized segment dimensions suitable for fabrication processes.
Solution Approach 2:
The patent optimizes interconnect parameters including segment length, width, spacing, and layer stacking to balance electrical performance with manufacturing capabilities. These parameters are selected to ensure segments remain within manufacturable length limits while achieving the required current supply stability through the collective mesh structure.
Data Source
AI summary
In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.