Power Isolation Wall Conductive Routing Stacked Transistors
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to efficiently route metal connections between upper and lower device layers in vertically stacked transistor devices without increasing the cross-sectional footprint, which is crucial for maintaining density and performance in advanced technology nodes.
Innovation Solution
The implementation of a power isolation wall filled with a conductive material, such as tungsten, copper, or titanium nitride, that extends from the upper device layer to the lower device layer, allowing for electrical connections between transistors while maintaining the compact footprint of the stacked structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal routing methods are used between device layers, then electrical connections can be established, but the cross-sectional footprint increases
Solution Approach 1:
The patent combines the isolation wall structure with the metal routing function by filling the isolation wall cavity with conductive material. This merging of isolation and interconnection functions eliminates the need for separate via structures, thereby establishing electrical connections between device layers without increasing the cross-sectional footprint.
Solution Approach 2:
The isolation wall is designed to serve multiple functions: it provides electrical isolation between adjacent transistors while simultaneously serving as the routing path for metal connections between device layers. This multi-functionality resolves the contradiction by eliminating the need for additional space-consuming via structures.
2Productivity
If device density is increased through vertical stacking, then capacity is improved, but routing complexity between layers increases
Solution Approach 1:
The patent merges the isolation wall and metal routing path into a single integrated structure. By filling the isolation wall cavity with conductive material, the design eliminates the need for separate via structures and complex multi-layer routing, thereby reducing routing complexity while maintaining high device density through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient power and signal routing between device layers without increasing the device's footprint, thereby supporting high-density and high-performance integrated circuits.
Implementation Method 1
the power isolation wall is filled with a conductive material that routes power between the upper device layer and the lower device layer
Data Source
AI summary
An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.