Multi-Layer Power Line Arrangement for Memory IR Drop Reduction
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing current-resistance (IR) drop due to the arrangement of power lines, which affects the efficient transfer of operating voltages for data access and processing.
Innovation Solution
A power line arrangement method that involves arranging power lines and ground lines in multiple layers with perpendicular track lines, allowing for electrical connections between layers through vias, and utilizing white spaces after signal routing to optimize power line placement and reduce IR drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power lines are arranged in conventional layouts, then the device structure is simple, but IR drop increases
Solution Approach 1:
The patent transitions from two-dimensional planar power line arrangement to three-dimensional arrangement by utilizing multiple layers. Power lines are distributed across different layers (first layer, second layer, third layer) with perpendicular track line orientations, effectively adding a vertical dimension to the power distribution network. This multi-layer approach reduces current path length and resistance without significantly increasing overall device complexity.
Solution Approach 2:
The power distribution network is segmented into multiple independent layers, each with its own track lines oriented in different directions. The first layer has track lines in a first direction, the second layer has track lines in a second direction perpendicular to the first, and the third layer has track lines in the first direction again. This segmentation allows optimized power delivery paths in each layer while maintaining manageable complexity through modular organization.
2Area of stationary object
If power lines are moved to adjacent track lines, then white space utilization improves, but routing complexity increases
Solution Approach 1:
When power lines need to be moved to adjacent track lines, the patent utilizes the vertical dimension by routing connections through different layers. This allows white space in one layer to be utilized without creating complex horizontal routing paths that would increase device complexity. The layered structure provides additional routing dimensions that simplify the overall design process.
Data Source
AI summary
A method of arranging power lines to be applied to a memory device including a plurality of layers, wherein, in each of the plurality of layers, a plurality of power lines and a plurality of signal lines are arranged along a plurality of track lines arranged side by side to be separated from each other in a first direction or a second direction that is perpendicular to the first direction is provided. The method includes identifying a first track line on which a plurality of power lines are arranged, moving at least one of the plurality of power lines to a second track line adjacent to the first track line, and electrically connecting the moved at least one power line on the second track line.