Hierarchical Power Management Subsystem Address Mapping
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Solution Overview
Problem
In modern computer systems with multiple circuit blocks operating at different power supply voltage levels, managing power resources across multiple power circuits is inefficient due to the need for multiple interfaces and increased compute resource diversion, leading to higher chip area and power consumption.
Innovation Solution
A power management subsystem organizes multiple power circuits in a hierarchical structure with a common address space, allowing a single communication interface to control multiple power circuits, reducing complexity and improving compute efficiency by mapping physical resources to a common address space and using a tree-like structure for command relay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple interfaces are used to control multiple power circuits, then each power circuit can be independently controlled, but chip area and device complexity increase
Solution Approach 1:
The patent implements a universal communication interface that can control multiple power circuits through a hierarchical address space. The host device uses a single interface to communicate with power circuits at different levels (root, intermediate, leaf) and locations within the hierarchical structure, eliminating the need for multiple dedicated interfaces while maintaining full control capability over all power circuits.
Solution Approach 2:
The patent introduces a hierarchical address space dimension to control power circuits. Instead of using multiple parallel interfaces, the system organizes power circuits in a hierarchical tree structure with levels and locations, allowing the single interface to navigate through this dimensional structure using address-based routing to reach any power circuit.
2Adaptability or versatility
If multiple interfaces are used to control multiple power circuits, then each power circuit can be independently controlled, but chip area increases
Solution Approach 1:
The patent implements a universal communication interface that can control multiple power circuits through a hierarchical address space. The host device uses a single interface to communicate with power circuits at different levels (root, intermediate, leaf) and locations within the hierarchical structure, eliminating the need for multiple dedicated interfaces while maintaining full control capability over all power circuits.
3Adaptability or versatility
If multiple interfaces are used to control multiple power circuits, then each power circuit can be independently controlled, but power consumption increases
Solution Approach 1:
The patent implements a universal communication interface that can control multiple power circuits through a hierarchical address space. The host device uses a single interface to communicate with power circuits at different levels (root, intermediate, leaf) and locations within the hierarchical structure, eliminating the need for multiple dedicated interfaces while maintaining full control capability over all power circuits.
4Device complexity
If a hierarchical structure with common address space is used, then communication complexity is reduced, but implementation complexity increases
Solution Approach 1:
The patent segments the power circuit control function into a hierarchical structure with root power circuits, intermediate power circuits, and leaf power circuits. Each level manages a specific subset of power circuits, and the hierarchical address space is divided into corresponding address ranges. This segmentation simplifies communication by allowing progressive routing through defined levels while maintaining manageable implementation through standardized interfaces and address mapping.
Data Source
AI summary
A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.


