Power Management Circuit Selective Cache Invalidation
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Solution Overview
Problem
Modern computer systems face increased resumption latency when power gating processor cores due to complete invalidation of instruction caches and translation lookaside buffers (TLBs), leading to inefficiencies in power management and increased costs.
Innovation Solution
Implementing a power management circuit with a storage module to track and selectively invalidate entries of instruction caches and TLBs based on received invalidation requests, allowing only a subset of entries to be invalidated before resuming normal execution, thus reducing the need for full cache and TLB rebuilding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complete invalidation of instruction caches and TLBs is performed before power gating processor cores, then power management reliability is improved, but resumption latency increases
Solution Approach 1:
The patent segments the invalidation process by tracking invalidation requests in a storage module and selectively invalidating only specific cache and TLB entries rather than performing complete invalidation. This segmentation allows the system to maintain reliability by invalidating necessary entries while avoiding the time penalty of invalidating all entries, thus resolving the contradiction between reliability and resumption latency.
Solution Approach 2:
The patent implements preliminary tracking of invalidation requests in a storage module before power gating occurs. By recording which entries need invalidation in advance, the system can perform targeted invalidation during resumption rather than complete invalidation, reducing resumption latency while ensuring that all necessary invalidations are performed for power management reliability.
2Reliability
If complete invalidation of instruction caches and TLBs is performed before power gating processor cores, then data consistency is improved, but power consumption increases
Solution Approach 1:
The patent segments the invalidation operation to affect only specific cache and TLB entries identified through tracking, rather than invalidating all entries. This selective approach maintains data consistency for modified entries while avoiding the excessive power consumption associated with complete invalidation and rebuilding of entire caches and TLBs during power gating operations.
Solution Approach 2:
The patent changes the parameter of invalidation scope from complete to selective based on tracked requests. By modifying this parameter, the system achieves data consistency through targeted invalidation while significantly reducing the power consumption that would result from complete cache and TLB rebuilding operations.
3Loss of time
If selective invalidation tracking is implemented, then resumption latency is reduced, but device complexity increases
Solution Approach 1:
The patent introduces a storage module as an intermediary component to track invalidation requests. This intermediary structure enables selective invalidation that reduces resumption latency while containing the increase in device complexity to a manageable level through a dedicated tracking mechanism rather than complex invalidation logic distributed throughout the entire system.
Data Source
AI summary
Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.