Power Management Circuitry for Data Processing Apparatus

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Solution Overview

Problem

The increasing performance gap between highest and lowest loading in data processing apparatuses leads to the need for more powerful power supplies, increasing cost and size, while voltage and frequency scaling impacts throughput, necessitating a method to reduce power consumption without significant voltage and frequency reduction.

Innovation Solution

Implementing power management circuitry that controls voltage supply and clock signal frequency to restrict the execution of high power events, thereby managing power consumption by throttling their execution, allowing lower-rated power supplies to be used while maintaining throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If voltage and frequency scaling is used to limit power consumption, then power consumption is reduced, but throughput is impacted as instructions are slowed down

Engineering Contradiction:
Improvepower consumptionVSAvoidthroughput
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent segments the event stream into high power events and normal events, applying different handling strategies to each. High power events are identified and tracked separately, allowing selective restriction of their execution while permitting normal events to proceed at full speed, thus reducing overall power consumption without significantly impacting throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts the restriction of high power event execution based on tracked metrics. The system monitors the frequency and pattern of high power events and adaptively controls their execution rate, creating a dynamic balance between power consumption and throughput rather than applying static voltage/frequency scaling.

Inventive Principle:
Principle #15Dynamics

2Power

If more powerful power supplies are provided to handle worst-case loading, then sufficient power is available for highest loading scenarios, but cost and size of the data processing apparatus increase

Engineering Contradiction:
Improvepower supply capacityVSAvoidsize of power supply
Core Design Contradiction:
PowerVSWeight of stationary object

Solution Approach 1:

The patent applies partial action by restricting only the execution of high power events rather than uniformly scaling back all operations. This selective approach allows the system to operate with a smaller power supply capacity than would be required for worst-case scenarios, since the high power events are throttled to prevent exceeding the reduced power supply's capacity.

Inventive Principle:
Principle #16Partial or excessive action

3Power

If more powerful power supplies are provided to handle worst-case loading, then sufficient power is available for highest loading scenarios, but cost of the data processing apparatus increases

Engineering Contradiction:
Improvepower supply capacityVSAvoidcost of apparatus
Core Design Contradiction:
PowerVSEase of manufacture

Solution Approach 1:

The patent applies partial action by restricting only the execution of high power events rather than uniformly scaling back all operations. This selective approach allows the system to operate with a smaller power supply capacity than would be required for worst-case scenarios, since the high power events are throttled to prevent exceeding the reduced power supply's capacity.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11409349B2Power management
Publication Date: 2022.08.09 ARM LTD
  • US11409349B2 patent drawing
  • US11409349B2 patent drawing
  • US11409349B2 patent drawing

AI summary

A data processing apparatus includes processing circuitry to process an event stream that includes one or more high power events. Tracking circuitry tracks the one or more high power events and power management circuitry manages power consumption by controlling a voltage supply and a frequency of a clock signal provided to the processing circuitry. The power management circuitry controls an extent to which execution by the processing circuitry of the high power events is restricted.