Power Management Controller for Processor Clusters

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Solution Overview

Problem

Current power management controllers (PMCs) face challenges in compatibility across different computing systems and integrated circuits, leading to inefficient power state transitions, oscillations, and increased power consumption due to multiple pending transitions and varying performance limits.

Innovation Solution

A power management controller that detects timing signals to calculate total power consumption, determines performance metrics, and adjusts processor clusters' power states by comparing these metrics to predefined limits, allowing for efficient power state transitions and reducing oscillations by predicting power consumption and merging pending transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If current power management controllers are used to manage power states, then power state transitions can be performed, but compatibility issues across different computing systems lead to oscillations and increased power consumption

Engineering Contradiction:
Improvecompatibility across computing systemsVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent implements a universal power management controller that can operate across different computing system architectures by providing a standardized interface and methodology for power state transitions. The controller uses a common set of performance metrics and limits that can be applied universally, while still accommodating architecture-specific characteristics through configurable parameters.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs feedback mechanisms by continuously monitoring performance metrics (such as power consumption, temperature, and performance levels) and using this information to dynamically adjust power state transitions. The controller compares actual performance against predefined limits and adjusts transitions accordingly, preventing oscillations by learning from system responses to previous transitions.

Inventive Principle:
Principle #23Feedback

2Speed

If multiple pending power state transitions are allowed, then system responsiveness can be improved, but oscillations occur leading to increased power consumption

Engineering Contradiction:
Improvesystem responsivenessVSAvoidpower consumption
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent allows multiple pending power state transitions to be queued in advance, preparing the system for upcoming power state changes before they are actually needed. This preliminary action enables the system to respond more quickly to changing conditions while maintaining control over the transition sequence, preventing oscillations by carefully managing when transitions are executed versus when they are merely prepared.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If performance limits are varied for different processor clusters, then system optimization can be improved, but compatibility and ease of management deteriorate

Engineering Contradiction:
Improvesystem optimizationVSAvoidmanagement complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent enables different performance limits to be configured for different processor clusters or cores, allowing each unit to be optimized for its specific workload and characteristics. However, this is achieved through a unified management framework that provides a consistent interface and methodology, reducing the apparent complexity for system managers while maintaining the ability to apply localized optimizations.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10656700B2Power management in an integrated circuit
Publication Date: 2020.05.19 ORACLE INT CORP
  • US10656700B2 patent drawing
  • US10656700B2 patent drawing
  • US10656700B2 patent drawing

AI summary

A power management controller is disclosed. Broadly speaking, the controller may, in response to detecting a timing signal, determine a total power consumption for a plurality of processor clusters, each of which includes a plurality of processor cores. The controller may determine a performance metric using the total power consumption and compare the performance metric to a limit. Based on a result of the comparison, the controller may select a new power state for at least one of the processor clusters.