Power Management System Synchronizing Device States with CPU Intervals
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Solution Overview
Problem
In computing platforms, especially mobile ones, power consumption is high due to the unpredictability of device interrupts and bus master traffic, limiting opportunities for reducing power consumption beyond periodic CPU power cycling.
Innovation Solution
A power management system that introduces additional device states and platform modes synchronized with CPU wakeup intervals, allowing for deterministic idle times and power gating of peripheral devices and system resources, thereby reducing power consumption beyond just CPU power cycling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If device interrupts and bus master traffic are handled with high responsiveness, then system reliability is improved, but power consumption increases because devices must remain in a state of readiness
Solution Approach 1:
The patent applies dynamics by introducing multiple power states (D0, D1, D2, D3) for devices, allowing them to transition between active and low-power states based on actual activity needs. Devices dynamically adjust their operational state rather than remaining statically in a high-power ready state, resolving the contradiction between responsiveness and power consumption.
Solution Approach 2:
The patent implements periodic action through defined idle windows synchronized with CPU wakeup intervals. During these periodic idle windows, devices can enter low-power states knowing that the CPU will be inactive, while still maintaining the ability to respond to interrupts outside these windows. This periodic structure allows power savings without sacrificing overall system responsiveness.
2Loss of time
If devices remain in a state of readiness to handle unpredictable interrupts, then interrupt response time is improved, but opportunities for power reduction are limited
Solution Approach 1:
The patent applies local quality by allowing different devices to be in different power states simultaneously based on their individual activity patterns and interrupt requirements. Not all devices must remain in the same state; each device can optimize its power state locally according to its specific needs, enabling power reduction without compromising overall interrupt response capability.
Solution Approach 2:
The patent uses preliminary action by defining idle windows in advance and synchronizing device power states with these predetermined time intervals. Devices prepare to enter low-power states during these pre-defined idle windows, knowing ahead of time when the CPU will be inactive. This preliminary planning allows power reduction while maintaining the ability to respond to interrupts that occur outside these windows.
3Loss of energy
If CPU is powered down periodically to reduce power consumption, then power savings are achieved, but other subsystems must remain active limiting overall power reduction
Solution Approach 1:
The patent merges the power management of the CPU with the power management of peripheral devices by synchronizing device idle states with CPU wakeup intervals. Instead of managing CPU and devices independently, the system combines their power management cycles, allowing devices to enter low-power states during CPU idle windows. This merging amplifies the overall power savings effect.
Solution Approach 2:
The patent creates a universal power management framework that applies to both the CPU and peripheral devices through synchronized idle windows. The same time intervals serve dual purposes: CPU wakeup intervals and device idle windows, creating a multi-functional power management system that coordinates power savings across the entire platform rather than treating components separately.
Data Source
AI summary
A power management system for a computing platform is described. In one embodiment, the power management system provides additional device states which the device controllers of the platform assume when the device controllers are operational but idle. These additional device states are states in which the device controller commits to certain types of inactivity. In another embodiment, the power management system provides additional platform modes which guarantee processor inactivity and/or deference of particular platform events while the mode is in effect.