Power Management Circuit Guard-Bit Validation for Register Access
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Solution Overview
Problem
Existing electronic devices face issues with incorrect register access and operation due to overlapping address ranges between different PMIC generations, leading to abnormal device operation and incorrect register writing.
Innovation Solution
Implementing a data frame with guard bits to identify the PMIC generation, ensuring the processor generates addresses using corresponding header files, and a decoder determines the legitimacy of the address based on these guard bits to prevent incorrect register access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the processor generates addresses using pre-built header files for different PMIC generations, then the processor can access registers in PMICs of various generations, but the address ranges of registers in PMICs with different generations overlap causing incorrect register access
Solution Approach 1:
The patent applies preliminary action by inserting guard bits into the address data frame before transmission to the PMIC. These guard bits are prepared in advance based on the PMIC generation type, enabling the PMIC to validate addresses before register access operations occur. This preliminary validation prevents incorrect register access caused by overlapping address ranges between different PMIC generations.
Solution Approach 2:
The patent uses guard bits as an intermediary element between the processor and the PMIC register access mechanism. These intermediary bits carry generation-specific information that mediates the address validation process, allowing the PMIC to distinguish between different generation types and correctly interpret addresses even when address ranges overlap across generations.
2Ease of operation
If the processor uses a wrong header file to generate addresses, then the processor can attempt to access registers, but the register is read or written incorrectly resulting in abnormal operation
Solution Approach 1:
The patent applies preliminary anti-action by implementing a validation mechanism that prevents incorrect register operations before they can occur. The guard bits in the address data frame serve as a preventive measure that blocks erroneous register reads or writes by detecting mismatches between the expected and actual PMIC generation types, thereby counteracting the potential harm of using wrong header files.
Solution Approach 2:
The patent implements feedback through the PMIC's validation of guard bits in received address data frames. When the PMIC detects that the guard bits do not match the expected pattern for its generation type, it provides feedback by rejecting the address validation, preventing incorrect register access. This feedback mechanism ensures operational correctness by continuously verifying address legitimacy.
Data Source
AI summary
An electronic system is provided. The electronic system includes a processor and a first power management circuit. The processor generates and outputs a first data frame. The first data frame includes at least one first guard bit and a first address. The first power management circuit includes a first register. The first power management circuit receives the first data frame and determines legitimacy of the first address according to the least one first guard bit. In response to that the first address is legal, the power management circuit transmits a first response to the processor and accesses a first region in the first register according to the first address.