Power Management Circuit Dynamic In-Rush Current Control
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Solution Overview
Problem
Conventional power management circuits in memory devices experience significant dynamic in-rush current and leakage issues during transitions from sleep to wake modes due to daisy chaining of control inputs and large area consumption, complicating timing and data integrity.
Innovation Solution
A power management circuit with a current limiting unit and a voltage drop minimization unit, where the voltage drop minimization unit has a greater number of sleep mode devices than the current limiting unit, and a sequential enabling unit generates non-overlapping control signals to turn on the voltage drop minimization unit after the current limiting unit with a predetermined delay, minimizing in-rush current and voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If daisy chaining of control inputs is used to control sleep mode transistors, then a single control signal can traverse the memory device, but large area consumption and complicated timing occur
Solution Approach 1:
The patent divides the sleep mode transistors into two separate groups: a first group connected to the local power supply rail and a second group connected to the global power supply rail. This segmentation eliminates the need for daisy-chained control signals to traverse the entire memory device, reducing the area required for control circuitry while maintaining the ability to control power distribution across different regions.
2Device complexity
If daisy chaining of control inputs is used, then power management is simplified, but timing determination becomes complicated
Solution Approach 1:
The patent employs a two-stage activation approach where the first group of sleep mode transistors is turned on before the second group. This preliminary action allows the local power supply rail to be established first, providing a stable reference voltage before the global power supply rail is activated, thereby simplifying timing determination and avoiding complex synchronization requirements.
3Loss of energy
If sleep transistors are used to cut off power supplies during sleep mode, then leakage current is minimized, but large in-rush current occurs during wake up transition
Solution Approach 1:
The patent activates the first group of sleep mode transistors (connected to local power supply) before activating the second group (connected to global power supply). This preliminary action allows the local power supply rail to be established first with controlled current, preventing the simultaneous activation that would cause large in-rush current while maintaining effective leakage blocking during sleep mode.
4Power
If voltage drop minimization is achieved with more sleep mode devices, then power delivery is improved, but in-rush current increases
Solution Approach 1:
The patent segments the sleep mode transistors into two groups with different quantities: a first group with a certain number of devices for current control, and a second group with a greater number of devices for voltage drop minimization. By activating the first group before the second group, the patent achieves both adequate power delivery capability and controlled in-rush current during the transition.
Data Source
AI summary
Disclosed are a circuit and a method for controlling dynamic in-rush current in a power management circuit. The circuit includes a current limiting unit having a first quantity of sleep mode devices. A voltage drop minimization unit is coupled to the current limiting unit and has a second quantity of sleep mode devices. The second quantity of sleep mode devices is greater than the first quantity of sleep mode devices. A sequential enabling unit is coupled to both the current limiting unit and the voltage drop minimization unit. The sequential enabling unit is configured to turn on the voltage drop minimization unit after the current limiting unit in accordance with a predetermined delay.