Power Management Module With Timing-Error-Driven DVFS
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Solution Overview
Problem
Current power management techniques for mobile devices are inefficient in reducing power consumption, particularly due to high leakage currents and error-induced voltage and frequency adjustments, which lead to increased energy consumption and error rates.
Innovation Solution
A device and method for power management that includes a power management module capable of detecting timing errors and adjusting the clock signal frequency and supply voltage by delaying the clock signal by a fraction of a cycle, allowing for dynamic voltage and frequency scaling based on load and error indications, thereby optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If aggressive DVS techniques are used to reduce power consumption by lowering voltage and clock frequency, then energy consumption is reduced, but error rates dramatically increase
Solution Approach 1:
The patent implements dynamic voltage and frequency scaling (DVFS) that adapts operating parameters in real-time based on computational load and error feedback. The system dynamically adjusts voltage and clock frequency levels, transitioning between high-performance mode and low-power mode with error correction, rather than using fixed aggressive scaling.
Solution Approach 2:
The patent introduces error detection and correction feedback mechanisms that monitor computational errors and adjust operating parameters accordingly. When errors are detected at low voltage/frequency levels, the system feedback-controls the operating point to prevent error accumulation, enabling safe operation in low-power regions while maintaining reliability.
2Use of energy by moving object
If voltage and clock frequency are lowered to reduce power consumption, then energy consumption decreases, but timing errors increase
Solution Approach 1:
The system dynamically adjusts voltage and clock frequency based on computational load and error feedback, allowing operation at lower voltages/frequencies when timing margins permit while maintaining timing accuracy through adaptive control and error correction mechanisms.
Solution Approach 2:
The patent changes operating parameters (voltage, clock frequency) based on computational load and error detection results. The system selectively adjusts these parameters to optimize the trade-off between energy consumption and timing precision, using error correction to enable operation at parameter values that would otherwise cause timing errors.
3Use of energy by moving object
If higher threshold voltage transistors are used to reduce leakage current, then power consumption decreases, but processing speed decreases
Solution Approach 1:
The patent implements dynamic operating mode selection that transitions between high-speed mode (using lower Vt transistors) and low-power mode (using higher Vt transistors or reduced voltage/frequency operation). The system adapts transistor operating characteristics dynamically based on computational requirements and error feedback.
Solution Approach 2:
The system changes operating parameters including voltage level and clock frequency to optimize the trade-off between leakage power and processing speed. By operating at reduced voltage/frequency with error correction, the system can use higher Vt transistors for lower leakage while maintaining acceptable performance through parameter adaptation.
4Reliability
If error correction mechanisms are added to aggressive DVS systems, then reliability improves, but device complexity increases
Solution Approach 1:
The patent implements error detection feedback mechanisms that monitor computational errors and control operating parameters accordingly. The feedback system adjusts voltage, frequency, or operational mode based on detected errors, enabling reliable low-power operation without requiring complex redundant circuitry throughout the entire system.
Solution Approach 2:
The patent introduces error detection and correction circuits as intermediary components that mediate between the computational units and the power management system. These intermediaries detect errors and trigger appropriate corrective actions (parameter adjustments, retries, or mode transitions) without requiring fundamental redesign of the core computational architecture.
Data Source
AI summary
A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting a timing error; delaying by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining a clock signal frequency and a level of the supply voltage in response to at least one detected timing error.