Power Management Unit for Nonvolatile Memory State Preservation
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Solution Overview
Problem
Computing devices face challenges in retaining CPU state during deep low power modes, requiring manual reset and lengthy initialization processes, which consume time and battery resources upon wake-up.
Innovation Solution
A hardware-based power management unit triggers storage of CPU and peripheral state information in non-volatile memory before entering low power mode, allowing for quick and power-efficient restoration upon wake-up without a full CPU reset, using an energy storage unit to ensure data integrity and availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the device enters deep low power mode by powering off the CPU, then power consumption is reduced, but the CPU state is lost requiring full reset and lengthy initialization
Solution Approach 1:
The system performs preliminary actions by saving CPU state to non-volatile memory before entering deep low power mode. The power management unit triggers storage of data from volatile storage elements to non-volatile memory in advance, so that upon wake-up the CPU can be quickly restored without full initialization sequences.
2Use of energy by moving object
If the device enters deep low power mode by powering off the CPU, then power consumption is reduced, but the device complexity increases due to hardware power management unit and energy storage requirements
Solution Approach 1:
The power management unit acts as an intermediary component that coordinates between the CPU, volatile memory, and non-volatile memory. It monitors power conditions, triggers state saving operations, and manages the transition to and from deep low power mode, thereby enabling power savings without requiring complex software power management.
3Reliability
If manual reset and initialization processes are performed upon wake-up, then the CPU state is restored, but power and time resources are consumed
Solution Approach 1:
The system creates a copy of the CPU state in non-volatile memory before entering deep low power mode. Upon wake-up, this copied state is restored to volatile memory, avoiding the need for full initialization sequences while ensuring reliable CPU state restoration. This copying approach consumes significantly less power than complete re-initialization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time and power consumption required for device startup, maintains stable operation by preserving CPU and peripheral states, and allows for quicker wake-up from low power modes, enhancing overall device stability and efficiency.
Implementation Method 1
The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode
Data Source
AI summary
A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.