Power Mesh Optimization Using Additional Wires for Voltage Drop Reduction
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Solution Overview
Problem
Clock tree synthesis methods often introduce issues like voltage drop and electromagnetic interference, which are difficult to address effectively, especially in crowded regions, leading to time-consuming error detection and potential impossibility of finding solutions.
Innovation Solution
A method and apparatus for power mesh optimization using additional wires, where clock cells are classified by size and enhanced with additional wires to create an optimal power mesh, reducing voltage drop and electromagnetic interference without introducing significant side effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If clock tree synthesis methods are used, then clock distribution is achieved, but voltage drop and electromagnetic interference problems occur
Solution Approach 1:
The patent segments the power mesh into multiple sub-meshes by inserting cut cells, which divide the original large power mesh into smaller manageable sections. This segmentation allows for better control of voltage drops and electromagnetic interference in each segment while maintaining overall clock distribution functionality.
Solution Approach 2:
The patent introduces cut cells as intermediary elements that act as buffers between different regions of the clock tree. These cut cells serve as mediators to isolate electromagnetic interference and prevent voltage drops from propagating across the entire power mesh, thereby reducing harmful effects while maintaining clock signal integrity.
2Measurement precision
If error detection is performed in late design phase, then problems are identified, but detection time increases significantly
Solution Approach 1:
The patent performs preliminary power mesh optimization during the clock tree synthesis phase by automatically inserting cut cells and optimizing power mesh parameters before final design completion. This preliminary action prevents voltage drop and EMI problems from occurring in the first place, eliminating the need for time-consuming error detection and correction in later design phases.
3Object-affected harmful factors
If additional wires are added to power mesh, then voltage drop and EMI are reduced, but device complexity increases
Solution Approach 1:
Instead of adding numerous additional wires throughout the entire power mesh, the patent segments the power mesh into sub-meshes using cut cells. This segmentation approach reduces the need for additional wires by creating isolated sections that naturally contain and manage electromagnetic interference and voltage drops, thereby reducing device complexity while still achieving the desired performance improvements.
Data Source
AI summary
A method for performing power mesh optimization with the aid of additional wires and an associated apparatus are provided. The method includes: reading a clock cell definition file to obtain respective basic information of a plurality of clock cells in a circuit design; and according to the respective basic information of the plurality of clock cells, executing a power mesh optimization procedure, including: regarding any type of clock cells in multiple types of clock cells within the plurality of clock cells, classifying the clock cells into a plurality of sub-types according to respective sizes of the type of clock cells; and performing power mesh enhancement on respective clock cells of a set of sub-types within the plurality of sub-types, to add a set of additional wires crossing a set of original wires in an original power mesh at each clock cell of any sub-type of the set of sub-types.