Integrated Power Module Back-Contact Resistor Gate Loop Oscillation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated power modules with parallel transistor configurations suffer from gate loop oscillations due to unbalanced device characteristics and asymmetric layouts, leading to potential short-circuits and malfunctions, and require additional gate resistors that increase loop inductance.
Innovation Solution
The integration of back-contact resistors with a flat planar structure on the shared gate conductor trace, connected to transistor chips via wire bonds, reduces loop inductance and oscillations, allowing for more symmetrical and efficient layouts with fewer connectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistor chips are arranged in parallel configuration, then power handling capability is improved, but gate loop oscillations occur due to unbalanced device characteristics and asymmetric layout
Solution Approach 1:
The patent applies asymmetry principle by intentionally designing the gate conductor trace layout to compensate for device characteristic variations. The gate conductor trace is routed to provide equal loop areas for each parallel transistor, creating a symmetrical magnetic field distribution that cancels out oscillations. This resolves the contradiction by transforming the asymmetric device characteristics into a balanced overall system through careful conductor trace geometry design.
Solution Approach 2:
The patent implements equipotentiality by ensuring that all gate-to-source loops have equal inductance values through symmetrical layout design. The gate conductor trace is positioned and dimensioned such that each parallel transistor experiences identical electrical conditions, eliminating potential differences that cause oscillations. This allows multiple devices to operate in parallel without the harmful effects of unbalanced gate voltages.
2Reliability
If separate gate conductor pads are used to complete loops, then oscillation damping is improved, but loop inductance increases due to longer gate loops
Solution Approach 1:
The patent merges the gate conductor trace with the common source conductor trace by positioning them in close proximity and routing them to form symmetrical loops. This integration allows the gate resistor to be placed on the common source side rather than requiring separate gate pads, thereby damping oscillations without significantly increasing loop inductance. The merged layout reduces the number of discrete connections while maintaining oscillation control.
3Ease of manufacture
If conventional asymmetric layout is used, then device mounting is simplified, but parasitic inductance increases and switching performance deteriorates
Solution Approach 1:
The patent uses asymmetry principle to design the gate conductor trace geometry that compensates for the asymmetric placement of parallel transistors. By carefully controlling the trace width, length, and positioning relative to each device, the layout achieves symmetrical electrical characteristics (equal loop inductance) while maintaining practical manufacturing simplicity. This resolves the contradiction between manufacturing ease and parasitic reduction.
Data Source
AI summary
An integrated power module having a dielectric substrate, a source conductor trace formed on the dielectric substrate, a drain conductor trace formed on the dielectric substrate, a gate conductor trace formed on the dielectric substrate, a transistor chip having a top surface and a bottom surface connected to the drain conductor trace, a back-contact resistor having a flat planar structure with a top surface and a bottom surface connected to the gate conductor trace, and a first wire bond connecting the top surface of the transistor chip to the top surface of the back-contact resistor.