Power Module Ceramic Substrate Heat Dissipation

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Solution Overview

Problem

Current power modules have a large volume and poor heat dissipation capabilities, which can lead to electronic device failure due to ineffective heat management as processing speed and performance increase.

Innovation Solution

The power module design incorporates a ceramic bonding substrate to isolate chips, utilizing its high thermal conductivity for improved heat dissipation, along with an interconnection layer for electrical signal transmission, and a lead frame for electrical connection, allowing for a thinner form factor and enhanced heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If a conventional power module structure with wires, lead frame and through mold processing is used, then the module can be manufactured with standard processes, but the module has a large volume and poor heat dissipation

Engineering Contradiction:
Improvepower module volumeVSAvoidheat dissipation ability
Core Design Contradiction:
Volume of moving objectVSTemperature

Solution Approach 1:

The patent transitions from traditional planar wire-based connections to a three-dimensional stacked architecture where chips are vertically arranged on the DBC substrate. This dimensional change reduces the horizontal footprint and allows heat to be conducted vertically through the thick copper layer, simultaneously achieving smaller volume and improved heat dissipation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs a composite structure combining DBC (direct bonded copper) substrate with thick copper heat dissipation layer, ceramic packaging material, and silicone rubber molding compound. This composite design integrates electrical connection, heat dissipation, and mechanical protection functions, resolving the contradiction between compact size and thermal management.

Inventive Principle:
Principle #40Composite materials

2Length of moving object

If the power module is made thinner to reduce volume, then the form factor is improved, but the heat dissipation ability may be compromised

Engineering Contradiction:
Improvemodule thicknessVSAvoidheat dissipation ability
Core Design Contradiction:
Length of moving objectVSTemperature

Solution Approach 1:

The patent reduces thickness in the horizontal plane while enhancing heat dissipation in the vertical dimension through the thick copper layer (50-200 micrometers) bonded to the DBC substrate. This directional heat conduction allows the module to be thinner overall while maintaining superior heat dissipation capability through the copper pathway.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies local quality enhancement by concentrating heat dissipation resources (thick copper layer) specifically at the chip contact areas and heat generation zones, rather than uniformly distributing material throughout the module. This localized approach reduces overall thickness while maintaining heat dissipation effectiveness where needed.

Inventive Principle:
Principle #3Local quality

3Volume of moving object

If chips are placed closer together to reduce volume, then packaging efficiency is improved, but the risk of short-circuit between chips increases

Engineering Contradiction:
Improvemodule volumeVSAvoidshort-circuit prevention
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent introduces the DBC substrate as an intermediary platform between chips, providing electrically isolated mounting positions through its ceramic substrate with embedded copper circuits. The ceramic material acts as an electrical insulator while thermally conductive path, allowing chips to be placed closely together without short-circuit risk while maintaining electrical independence.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

By arranging chips in a vertical stacked configuration rather than spreading them horizontally, the patent reduces the horizontal distance between chips while the vertical separation through the DBC substrate structure prevents electrical short-circuits. This dimensional reorganization allows high-density packaging with maintained reliability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces heat and electrical transmission distance, improving heat dissipation and packaging efficiency while preventing short-circuits, enabling the power module to maintain performance and reliability.

Implementation Method 1

utilizing its high thermal conductivity for improved heat dissipation

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

an interconnection layer for electrical signal transmission

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS10051742B2Power module and manufacturing method thereof
Publication Date: 2018.08.14 IND TECH RES INST
  • US10051742B2 patent drawing
  • US10051742B2 patent drawing
  • US10051742B2 patent drawing

AI summary

A power module and a manufacturing method thereof are provided, and the power module includes a carrier substrate, an interconnection layer, a first chip, a second chip, a ceramic bonding substrate, a top interconnection layer and a lead frame. The interconnection layer is disposed on the carrier substrate. The first chip and the second chip are disposed on the interconnection layer, and electrically connected to the interconnection layer. The ceramic bonding substrate is disposed on the interconnection layer, and is disposed in between the first chip and the second chip so as to separate the first chip from the second chip. The top interconnection layer is disposed on the ceramic bonding substrate, covers the first chip and the second chip, and is electrically connected to the first chip and the second chip. The lead frame is disposed on the top interconnection layer and electrically connected to the top interconnection layer.