Power Semiconductor Module Layout for Chip-Level Diagnostics
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Solution Overview
Problem
Multichip power semiconductor modules are limited in their ability to configure complex topologies and extract chip-level diagnostics due to basic terminal connections that do not allow for individual chip information extraction, leading to constraints in diagnostics and control.
Innovation Solution
A power semiconductor module design featuring a semiconductor board with multiple chips and an adapter board that allows for flexible topology configuration and diagnostics signal extraction through vertically connected terminals and auxiliary terminals, enabling various interconnections and advanced sensing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If power semiconductor chips are connected and controlled in parallel with basic terminal connections, then the module structure is simple, but the ability to extract chip-individual information and configure complex topologies is limited
Solution Approach 1:
The module divides the semiconductor board into multiple independent terminal areas, each associated with a specific semiconductor chip. Each terminal area provides separate power terminals and auxiliary terminals for individual chip access, enabling independent control and diagnostics while maintaining overall module integration
Solution Approach 2:
Auxiliary terminals serve as intermediary connection points between the semiconductor chips and the external circuitry. These auxiliary terminals enable extraction of chip-individual information such as temperature and current without requiring complex wiring, acting as mediators that simplify the interface between multiple chips and external diagnostic equipment
2Measurement precision
If separate terminals are provided for each semiconductor chip, then chip-individual diagnostics and control are enabled, but the module footprint and stray inductance increase
Solution Approach 1:
The module transitions from a planar two-dimensional layout to a three-dimensional structure by stacking the semiconductor board vertically with terminal areas arranged in rows and columns. This vertical arrangement allows multiple terminal areas to be compactly organized, reducing the horizontal footprint while providing separate access to each chip through the vertical dimension
Solution Approach 2:
Multiple terminal areas are merged into a single integrated semiconductor board structure, sharing common substrates and interconnection layers. This consolidation provides chip-individual terminals while maintaining a compact unified module design, avoiding the need for separate discrete modules for each chip
3Adaptability or versatility
If multiple terminal areas are arranged on the semiconductor board, then flexible topology configurations are enabled, but the manufacturing complexity increases
Solution Approach 1:
The semiconductor board is designed as a universal platform that can accommodate different topology configurations through its array of terminal areas. The same board structure with multiple terminal areas can be used for various topologies (half-bridge, full-bridge, three-level, etc.) by simply changing the connection configuration, eliminating the need for different specialized boards for different applications
Solution Approach 2:
The terminal areas and their associated power terminals and auxiliary terminals are pre-configured and positioned on the semiconductor board during manufacturing. This preliminary arrangement of terminals in standardized rows and columns allows for simplified assembly and connection processes, as the basic infrastructure is already in place before final topology-specific connections are made
Data Source
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AI summary
A power semiconductor module (10) comprises at least one semiconductor board (16) comprising at least two semiconductor chips (24), each semiconductor chip (24) having two power electrodes (26, 28); an adapter board (14) attached to the semiconductor board (16) above the at least two semiconductor chips (24), the adapter board (14) comprising a terminal area (46) for each semiconductor chip (24) on a side facing away from the semiconductor board (16); wherein the adapter board (14), in each terminal area (46), provides a power terminal (42) for each power electrode (26, 28) of the semiconductor chip (24) associated with the terminal area (46); wherein each power terminal (42) is electrically connected via an electrical conductive vertical post (34, 36) below the terminal area (46) with the semiconductor chip (24).