Power Semiconductor Module Layout for Isolating Damaged Parallel Chips
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Solution Overview
Problem
Existing power semiconductor modules face the risk of losing an entire package due to chip damage during manufacturing, leading to high production costs and low yield, particularly with wide band gap devices like SiC MOSFETs and GaN HEMTs, which have low current rating per chip and are often paralleled to achieve competitive current rating.
Innovation Solution
A method for manufacturing power semiconductor modules that involves measuring individual chips for damage, electrically interconnecting non-damaged chips in parallel, and separating damaged chips from the non-damaged ones to prevent them from interfering with the module's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple small power semiconductor devices are paralleled to achieve target current rating, then the current rating requirement is met, but the risk of losing entire package increases if one chip gets damaged
Solution Approach 1:
The patent applies segmentation by dividing the electrical connection system into independent zones. Conductive bonds are configured such that damaged chips are electrically isolated from functional chips through segmented bonding paths. This allows the module to be divided into operational and non-operational segments, preventing failure propagation across the entire module while maintaining the required current rating through parallel connection of functional devices.
2Reliability
If high requirements for manufacturing process are implemented to avoid chip losses, then chip damage risk is reduced, but production costs increase
Solution Approach 1:
The patent implements preliminary action by performing electrical separation of damaged chips during the manufacturing process before final module assembly and testing. By configuring conductive bonds to provide automatic electrical isolation of damaged chips early in the process, the invention prevents the need for costly rework or complete module rejection. This preliminary configuration of bonding paths enables early detection and isolation of failures, reducing scrap rates without requiring excessively stringent manufacturing controls.
3Ease of manufacture
If damaged chips are not separated from non-damaged chips, then manufacturing process is simpler, but entire module must be discarded when damage occurs
Solution Approach 1:
The patent introduces an intermediary electrical separation mechanism through specifically configured conductive bonds. These bonds act as intermediaries that automatically isolate damaged chips from the functional circuitry. The bonding structure itself serves as the separation mechanism, requiring no additional mechanical or electrical components. This intermediary approach maintains manufacturing simplicity while enabling automatic yield protection through electrical isolation of failed devices.
Data Source
AI summary
A power semiconductor module (34), comprising a substrate (12) which carries a plurality of power semiconductor devices (10), wherein the plurality of power semiconductor devices (10) comprises a first group of power semiconductor devices (10) and a second group of at least one power semiconductor device (10). The first group of power semiconductor devices (10) consists of at least two non-damaged power semiconductor devices (10b, 10c), and the second group of power semiconductor devices (10) consists of at least one damaged power semiconductor device (10a). The at least two non-damaged power semiconductor devices (10b, 10c) are electrically interconnected in a parallel configuration, and the second group of at least one power semiconductor device (10) is electrically separated from the members of the first group of power semiconductor devices (10).The disclosure further relates to an electrical converter and a method for manufacturing a power semiconductor module (34).