Power Module Chip Layout for Isolated Electrical Testing

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Solution Overview

Problem

In high-voltage power modules used in electric vehicles, the yield of semiconductor chips such as MOSFETs and IGBTs is low due to defects in electrical tests, where even non-defective chips are treated as defective, leading to decreased efficiency.

Innovation Solution

The semiconductor device is designed with a single semiconductor chip per insulating plate, using multiple metal plates and encapsulating materials to improve heat dissipation and electrical connectivity, reducing the likelihood of defective treatments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple semiconductor chips are mounted on a single insulating plate, then productivity increases, but reliability decreases due to defects in electrical tests treating non-defective chips as defective

Engineering Contradiction:
Improvemounting densityVSAvoidyield
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The insulating plate is divided into multiple mounting regions (first mounting region and second mounting region) separated by a groove. This segmentation isolates electrical test signals between regions, preventing false defect detections and enabling higher mounting density without compromising yield.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple semiconductor chips are mounted on a single insulating plate, then productivity increases, but manufacturing precision decreases due to electrical test interference

Engineering Contradiction:
Improvemounting densityVSAvoidelectrical test accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The groove physically divides the mounting areas, creating isolated electrical zones. This segmentation prevents signal interference during electrical testing, ensuring accurate defect detection even with multiple chips per plate.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The groove acts as an intermediary barrier between mounting regions, blocking electrical signal interference and enabling accurate testing of multiple chips simultaneously.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If heat dissipation is improved through additional metal plates, then reliability increases, but device complexity increases

Engineering Contradiction:
Improveheat dissipationVSAvoidstructure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The groove structure serves dual purposes: it separates mounting regions for electrical isolation and simultaneously functions as a heat dissipation pathway. This merging of functions improves reliability without proportionally increasing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The groove structure performs multiple functions: electrical isolation between regions and heat dissipation from the insulating plate. This multi-functionality achieves reliability improvement without adding separate dedicated components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the yield by avoiding non-defective chips from being classified as defective, thereby improving the overall efficiency and reliability of the semiconductor devices.

Implementation Method 1

a first metal plate provided on a first surface of the first insulating plate, a second metal plate provided on a second surface of the first insulating plate... the number of semiconductor chips provided on the second metal plate is only one

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20250210493A1Semiconductor device
Publication Date: 2025.06.26 KK TOSHIBA
  • US20250210493A1 patent drawing
  • US20250210493A1 patent drawing
  • US20250210493A1 patent drawing

AI summary

A semiconductor device according to an embodiment includes a first insulating plate, a first metal plate provided on a first surface of the first insulating plate, a second metal plate provided on a second surface of the first insulating plate opposite the first surface, a semiconductor chip provided on the second metal plate, and a resin member encapsulating the semiconductor chip. In this semiconductor device, the number of semiconductor chips provided on the second metal plate is only one.