Power Module Wiring Substrate Layout for Creepage and Area Reduction
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Solution Overview
Problem
Conventional power semiconductor modules require a wide insulating region on the control wiring substrate to maintain creepage insulation, leading to increased area usage and manufacturing complexity.
Innovation Solution
A semiconductor device configuration with a conductive substrate and a control wiring substrate featuring narrower bottom-surface conductive layers and wider top-surface conductive layers, reducing the overall area required for the control wiring substrate while maintaining effective insulation and connectivity between semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional control wiring substrate with uniform conductive layers is used, then electrical connectivity is maintained, but the area of the substrate increases and manufacturing complexity increases due to wide insulating regions being required
Solution Approach 1:
The patent applies local quality by making the bottom-surface conductive layers narrower than the top-surface conductive layers. This creates a tapered structure where the insulating layer has greater width at the bottom than at the top, providing enhanced creepage insulation distance at the critical bottom surface while maintaining electrical connectivity at the top surface. This localized variation in geometry resolves the contradiction by providing differential insulation characteristics in different regions of the same component.
2Reliability
If wider insulating regions are provided on the control wiring substrate, then creepage insulation distance is maintained, but the area of the substrate increases
Solution Approach 1:
The patent employs asymmetry by creating non-uniform conductive layer widths across the thickness of the substrate. The bottom-surface conductive layers are deliberately made narrower than the top-surface conductive layers, creating an asymmetric tapered structure. This asymmetric geometry allows the insulating layer to provide sufficient creepage insulation distance without requiring a uniformly wide substrate area throughout, thus reducing the overall substrate area while maintaining insulation reliability.
3Ease of manufacture
If lead frames and bonding wires are used to connect semiconductor chips, then electrical connectivity is achieved, but manufacturing complexity and substrate area increase
Solution Approach 1:
The patent merges the functions of the control wiring substrate and the connection structure by integrating the conductive layers directly into the substrate architecture. Instead of using separate lead frames and bonding wires to establish electrical connections, the conductive layers are formed as integral parts of the substrate, with the narrower bottom layers providing both structural support and electrical pathways. This merging eliminates the need for additional discrete components and simplifies the manufacturing process.
Solution Approach 2:
The patent transitions from a two-dimensional planar connection approach to a three-dimensional tapered structure. By varying the width of conductive layers through the thickness dimension of the substrate, the invention creates vertical differentiation that provides both insulation and connectivity functions within the substrate volume itself, rather than relying on separate horizontal components like lead frames and bonding wires.
Data Source
AI summary
A semiconductor device includes: a conductive substrate; a plurality of semiconductor chips each having a first main electrode on a bottom surface side and a second main electrode on a top surface side, the plural semiconductor chips being arranged to form a first column and a second column connected parallel to each other on the conductive substrate; and a control wiring substrate including an insulating layer, a plurality of top-surface conductive layers provided on a top surface of the insulating layer, and a plurality of bottom-surface conductive layers each having a narrower width than the insulating layer and provided on a bottom surface of the insulating layer, the bottom-surface conductive layers being arranged on the conductive substrate between the first column and the second column of the semiconductor chips.