Power Semiconductor Module Layout for Lower Current Density
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Solution Overview
Problem
Power semiconductor module arrangements face challenges in increasing current carrying capacity while maintaining a small substrate size, leading to high current density in areas with small cross-sectional areas, which can reduce the module's efficiency and lifespan.
Innovation Solution
A power semiconductor module arrangement with a structured first metallization layer and electrically conducting elements that increase the cross-sectional area of sub-sections, using a dielectric insulation layer and electrically conductive connection layers without semiconductor bodies, to distribute current more efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the substrate size is kept small to reduce cost, then the manufacturing cost is reduced, but the current density significantly increases in areas with small cross-sectional area
Solution Approach 1:
The patent applies dimensionality change by adding a vertical third dimension to the metallization structure. Instead of only expanding the substrate area horizontally, the invention stacks multiple metallization layers (first metallization layer, second metallization layer, and electrically conducting elements) vertically to increase the current carrying cross-sectional area. This allows the substrate to maintain a small footprint while achieving higher current capacity through increased vertical thickness of the conductive path.
2Reliability
If the cross-sectional area of metallization sections is increased to reduce current density, then the current carrying capacity is improved, but the substrate size significantly increases
Solution Approach 1:
The patent resolves this contradiction by transitioning from two-dimensional area expansion to three-dimensional volume utilization. Multiple metallization layers are stacked vertically with each layer contributing to the current carrying capacity. The total effective cross-sectional area for current flow becomes the sum of areas across all vertical layers, enabling high current capacity within a compact substrate footprint.
Solution Approach 2:
The invention employs a nested structure where the second metallization layer is positioned above and overlaps with portions of the first metallization layer, and electrically conducting elements are integrated within the housing structure. This nesting arrangement maximizes the use of vertical space and allows multiple conductive paths to coexist within a compact volume, increasing current capacity without proportionally increasing substrate area.
3Productivity
If integration density is increased to maintain small substrate size, then the substrate size is reduced, but the current density significantly increases in at least some sections
Solution Approach 1:
The patent addresses this contradiction by distributing current paths across multiple vertical layers. While integration density increases on each individual layer, the overall current density is reduced by spreading the current load across the cumulative cross-sectional area of all metallization layers. This vertical distribution allows high integration density to be achieved without causing excessive current density in any single section.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively increases the current carrying capacity and reduces current density in critical areas, enhancing the module's performance and longevity by ensuring larger cross-sectional areas for current flow.
Implementation Method 1
at least one semiconductor body arranged on and attached to the first metallization layer by means of an electrically conductive connection layer
Data Source
Figure 1~3B
Figure 4~6
AI summary
A power semiconductor module arrangement comprises a substrate (10) comprising a dielectric insulation layer (11), and a first metallization layer (111) arranged on a first surface of the dielectric insulation layer (11), at least one semiconductor body (20) arranged on and attached to the first metallization layer (111) by means of an electrically conductive connection layer (30), and at least one electrically conducting element (80) arranged on the first metallization layer (111), wherein the first metallization layer (111) is a structured layer comprising a plurality of different subsections, the first metallization layer (111) has a uniform thickness in a vertical direction (y), wherein the vertical direction (y) is perpendicular to the first surface of the dielectric insulation layer (11), each of the at least one electrically conducting element (80) is arranged on and covers a subarea of a sub-section, thereby increasing the cross-sectional area of the subarea of the respective sub-section, and each of the at least one electrically conducting element (80) comprises an electrically conductive connection layer (30) without a semiconductor body (20) arranged thereon.